Qualcomm Incorporated

Hyeokjin Lim

Venugopal Boynapalli

Xiangdong Chen

Foua Vang

Satyanarayana Sahu

Mukul Gupta

Mickael Malabry

Seung Hyuk Kang

Stanley Seungchul Song

Kern Rim

Bharani Chava

Haining S Yang

Jonghae Kim

Periannan Chidambaram

Giridhar Nallapati

Ohsang Kwon

Deepak Sharma

Peijie Feng

Qi Ye

Sorin Adrian Dobre

Zhengyu Duan

Raymond George Stephany

Renukprasad Hiremath

Radhika Vinayak Guttal

Lavakumar Ranganathan

Hadi Bunnalim

Chih-lung Kao

Jingwei Zhang

Robert Kim

Lesly Zaren V Endrinal

Rami Salem

Hananel Kang

Shitiz Arora

A MOS IC logic cell includes a plurality of gate interconnects extending on tracks in a first direction. The logic cell includes intra-cell routing interconnects coupled to at least a subset of the gate interconnects. The intra-cell routing interconnects include intra-cell Mx layer interconnects on an Mx layer extending in the first direction. The Mx layer is a lowest metal layer for PG extending in the first direction. The intra-cell Mx layer interconnects extend in the first direction over at least a subset of the tracks excluding every mtrack, where 2&#x2264;m&#x3c;Pand Pis a PG grid pitch. A MOS IC may include at least one MOS IC logic cell, and may further include a first set of PG Mx layer interconnects extending in the first direction over the at least one logic cell. The first set of PG Mx layer interconnects have the pitch P&#x3e;m*P.

Vertical power grid standard cell architecture

Field-effect transistor (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals. A FET circuit is provided that includes a FET that includes a conduction channel, a source, a drain, and a gate. The FET circuit also includes a topside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes a backside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes topside and backside metal lines electrically coupled to the respective topside and backside metal contacts to provide power and signal routing to the FET. A complementary metal oxide semiconductor (CMOS) circuit is also provided that includes a PFET and NFET that each includes a topside and backside contact for power and signal routing.

Field-effect transistors (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals, and related complementary metal oxide semiconductor (CMOS) circuits

Circuits employing a back side-front side connection structure for coupling back side routing to front side routing, and related complementary metal oxide semiconductor (CMOS) circuits and methods are disclosed. The circuit includes a front side metal line disposed adjacent to a front side of a semiconductor device for providing front side signal routing. The circuit also includes a back side metal line disposed adjacent to a back side of the semiconductor device for providing back side signal routing. In this manner, the back side area of the semiconductor device may be employed for signal routing to conserve area and/or reduce routing complexity. The circuit also includes a back side-front side connection structure that electrically couples the front side metal line to the back side metal line to support signal routing from the back side to the front side of the circuit, or vice versa to provide greater routing flexibility.

Circuits employing a back side-front side connection structure for coupling back side routing to front side routing, and related complementary metal oxide semiconductor (CMOS) circuits and methods

A MOS IC includes a MOS logic cell that includes first and second sets of transistor logic in first and second subcells, respectively. The first and second sets of transistor logic are functionally isolated from each other. The MOS logic cell includes a first set of Mlayer interconnects on an Mlayer extending in a first direction over the first and second subcells. A first subset of the first set of Mlayer interconnects is coupled to inputs/outputs of the first set of transistor logic in the first subcell and is unconnected to the second set of transistor logic. Each of the first subset of the first set of Mlayer interconnects extends from the corresponding input/output of the first set of transistor logic of the first subcell to the second subcell, and is the corresponding input/output of the first set of transistor logic.

Multibit multi-height cell to improve pin accessibility

A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first Mlayer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second Mlayer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second Mlayer interconnects are parallel. The MOS device further includes a first Mlayer interconnect extending in a second direction orthogonal to the first direction. The first Mlayer interconnect is coupled to the first Mlayer interconnect and the second Mlayer interconnect. The MOS device further includes a second Mlayer interconnect extending in the second direction. The second Mlayer interconnect is coupled to the first Mlayer interconnect and the second Mlayer interconnect. The second Mlayer interconnect is parallel to the first Mlayer interconnect.

Multiple via structure for high performance standard cells

Metal oxide semiconductor device of an integrated circuit

A chip includes a first gate extended along a second lateral direction, a first source electrically coupled to a power rail, and a first metal interconnect extended along a first lateral direction approximately perpendicular to the second lateral direction, wherein the first metal interconnect lies above the first gate and the first source, and the first metal interconnect is configured to electrically couple the first gate to the first source. The chip also includes a second gate extended along the second lateral direction, a second source electrically coupled to the power rail, and a second metal interconnect extended along the first lateral direction, wherein the second metal interconnect lies above the second gate and second source, the second metal interconnect is configured to electrically couple the second gate to the second source, and the first metal interconnect is aligned with the second metal interconnect in the second lateral direction.

Standard cell architecture for gate tie-off

In certain aspects of the disclosure, a cell includes a first dummy gate extended along a second lateral direction and on a boundary of the cell, a second dummy gate extended along the second lateral direction and on an opposite boundary of the cell, and a third gate extended along the second lateral direction, wherein the third gate is between the first dummy gate and the second dummy gate. The cell also includes a source between the second dummy gate and the third gate electrically coupled to a power rail. The cell further includes a metal interconnect extended along a first lateral direction approximately perpendicular to the second lateral direction and above the first dummy gate, the source, and the third gate, wherein the metal interconnect is configured to couple the first dummy gate to the power rail through the source.

In certain aspects, a semiconductor die includes a first doped region, a second doped region, and an interconnect formed from a first middle of line (MOL) layer, wherein the interconnect electrically couples the first doped region to the second doped region. The semiconductor die also includes a first metal line formed from a first interconnect metal layer, and a first via electrically coupling the interconnect to the first metal line.

High performance cell design in a technology with high density metal routing

A MOS IC includes a first standard cell including first and second power rails, first and second active regions, and a plurality of metal interconnects. The first power rail extends in a first direction and provides a first voltage to the first standard cell. The second power rail extends in the first direction and provides a second voltage to the first standard cell. The first active region is between the first and second power rails on a first side of the first standard cell. The second active region is between the first and second power rails on a second side of the first standard cell. The second active region is separated from the first active region. The plurality of metal interconnects extend in a second direction between the first and second active regions and between the first and second power rails. The second direction is orthogonal to the first direction.

Visible alignment markers/landmarks for CAD-to-silicon backside image alignment

According to certain aspects of the present disclosure, a chip includes a first gate, a second gate, a first source, a first source contact disposed on the first source, a metal interconnect above the first source contact and the first gate, a first gate contact electrically coupling the first gate to the metal interconnect, and a first via electrically coupling the first source contact to the metal interconnect. The chip also includes a power rail, and a second via electrically coupling the first source contact to the power rail. The second gate is between the first source and the first gate, and the metal interconnect passes over the second gate.

In certain aspects, a semiconductor die includes a first cell and a second cell. The first cell includes first transistors, and a first interconnect structure interconnecting the first transistors to form a first circuit. The second cell includes second transistors, and a second interconnect structure interconnecting the second transistors to form a second circuit. The first circuit and the second circuit are configured to perform a same function, and a length of the first cell in a first lateral direction is greater than a length of the second cell in the first lateral direction.

Placement methodology to remove filler

In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus for assigning feature colors for a multiple patterning process are provided. The apparatus receives integrated circuit layout information including a set of features and an assigned color of a plurality of colors for each feature of a first subset of features of the set of features. In addition, the apparatus performs color decomposition on a second subset of features to assign colors to features in the second subset of features. The second subset of features includes features in the set of features that are not included in the first subset of features with an assigned color.

Hybrid coloring methodology for multi-pattern technology

A MOS IC may include a first contact interconnect in a first standard cell that extends in a first direction and contacts a first MOS transistor source and a voltage source. Still further, the MOS IC may include a first double diffusion break extending along a first boundary in the first direction of the first standard cell and a second standard cell. The MOS IC may also include a second contact interconnect extending over a portion of the first double diffusion break. In an aspect, the second contact interconnect may be within both the first standard cell and the second standard cell and coupled to the voltage source. Additionally, the MOS IC may include a third contact interconnect extending in a second direction orthogonal to the first direction and couples the first contact interconnect and the second contact interconnect together.

Growing community of inventors

San Diego, CA, United States of America

Hyeokjin Lim