Samsung Electronics Co., Ltd.

Hwichan Jun

Inchan Hwang

Byounghak Hong

Seunghyun Song

Kang Ill Seo

A semiconductor device includes a substrate; a 1transistor formed above the substrate, and having a 1transistor stack including a plurality of 1channel structures, a 1gate structure surrounding the 1channel structures, and 1and 2source/drain regions at both ends of the 1transistor stack in a 1channel length direction; and a 2transistor formed above the 1transistor in a vertical direction, and having a 2transistor stack including a plurality of 2channel structures, a 2gate structure surrounding the 2channel structures, and 3and 4source/drain regions at both ends of the 2transistor stack in a 2channel length direction, wherein the 3source/drain region does not vertically overlap the 1source/drain region or the 2source/drain region, and the 4source/drain region does not vertically overlap the 1source/drain region or the 2source/drain region.

Crossing multi-stack nanosheet structure and method of manufacturing the same

A stacked semiconductor device includes: a substrate; a 1transistor formed on a substrate, and including a 1active region surrounded by a 1gate structure and 1source/drain regions; and a 2transistor stacked on the 1transistor, and including a 2active region surrounded by a 2gate structure and 2source/drain regions, wherein the 1active region and the 1gate structure are vertically mirror-symmetric to the 2active region and the 2gate structure, respectively, with respect to a virtual plane therebetween.

Stacked semiconductor device having mirror-symmetric pattern

A semiconductor device including a static random access memory (SRAM) in a three-dimensional (3D) stack is provided. The semiconductor device includes a first transistor stack including a first channel and a first gate, a second transistor stack including a second channel and a second gate, the second transistor stack being disposed above the first transistor stack, a bit line disposed on a first portion of an upper surface of the first channel, a voltage source disposed on a first portion of an upper surface of the second channel and a first shared contact connecting the first channel to the second channel, where a width of the second channel is less than a width of the first channel.

SRAM memory cell for stacked transistors with different channel width

A semiconductor device include: a substrate; a 1transistor formed above the substrate, the 1transistor including a 1channel set of a plurality of 1nanosheet layers, a 1gate structure surrounding the 1nanosheet layers, and 1and 2source/drain regions at both ends of the 1channel set; and a 2transistor formed above the 1transistor in a vertical direction, the 2transistor including a 2channel set of a plurality of 2nanosheet layers, a 2gate structure surrounding the 2nanosheet layers, and 3and 4source/drain regions at both ends of the 2channel set, wherein the 1channel set has a greater width than the 2channel set, wherein a number of the 1nanosheet layers is smaller than a number of the 2nanosheet layers, and wherein a sum of effective channel widths of the 1nanosheet layers is substantially equal to a sum of effective channel width of the 2nanosheet layers.

Semiconductor device having stepped multi-stack transistor structure

An array of multi-stack transistor structures is provided, wherein the multi-stack transistor structures are arranged in a plurality of rows and a plurality of columns in the array, wherein each of the multi-stack transistor structures includes two or more vertically arranged transistor stacks, and wherein a dam structure is formed between adjacent two rows in a same column so that a multi-stack transistor structure in one of the adjacent two rows is electrically isolated from a multi-stack transistor structure in the other of the adjacent two rows in the same column.

Growing community of inventors

Clifton Park, NY, United States of America

Hwichan Jun