Mosel Vitelic Corporation

Other

Huoy-Jong Wu

Kuo-Tung Sung

Chung-Cheng Wu

Li-Chun Li

Saysamone Pittikoun

Wen-Wei Lo

Wen-Ting Chu

Dynamic Random Access Memory (DRAM) cells are formed in a P well formed in a biased deep N well (DNW). PMOS transistors are formed in N wells. The NMOS channels stop implant mask is modified not to be a reverse of the N well mask in order to block the channels stop implant from an N&plus; contact region used for DNW biasing. In DRAMs and other integrated circuits, a minimal spacing requirement between a well of an integrated circuit on the one hand and adjacent circuitry on the other hand is eliminated by laying out the adjacent circuitry so that the well is located adjacent to a transistor having an electrode connected to the same voltage as the voltage that biases the well. For example, in DRAMs, the minimal spacing requirement between the DNW and the read/write circuitry is eliminated by locating the DNW next to a transistor precharging the bit lines before memory accesses. One electrode of the transistor is connected to a precharge voltage. This electrode overlaps the DNW which is biased to the same precharge voltage. This electrode provides the DNW N&plus; contact region.

Method for fabricating an integrated circuit with a transistor electrode

Dynamic Random Access Memory (DRAM) cells are formed in a P well formed in a biased deep N well (DNW). PMOS transistors are formed in N wells. The NMOS channels stop implant mask is modified not to be a reverse of the N well mask in order-to block the channels stop implant from an N&plus; contact region used for DNW biasing. In DRAMS and other integrated circuits, a minimal spacing requirement between a well of an integrated circuit on the one hand and adjacent circuitry on the other hand is eliminated by laying out the adjacent circuitry so that the well is located adjacent to a transistor having an electrode connected to the same voltage as the voltage that biases the well. For example, in DRAMs, the minimal spacing requirement between the DNW and the read/write circuitry is eliminated by locating the DNW next to a transistor precharging the bit lines before memory accesses. One electrode of the transistor is connected to a precharge voltage. This electrode overlaps the DNW which is biased to the same precharge voltage. This electrode provides the DNW N&plus; contact region.

An E,PROM or a flash memory cell having a sharp tip or thin wedge at one of its gates, e.g., the floating gate, for the erasure of electrical charges stored in the floating gate. A recess is formed between a first polysilicon gate and the substrate by removing portions of an insulating layer interposed between the first gate and the substrate. Another insulating layer, e.g., thermal oxide, is formed on the exposed portions of the first gate and the substrate, and partially fills the recess. A second polysilicon layer is formed on the thermal oxide and patterned to form a floating gate. The partially filled recess causes a sharp polysilicon tip or thin wedge to be formed as part of the floating gate. This sharp tip or thin wedge can generate a high electrical field that facilitates the removal of the stored electrical charges from the floating gate.

Memory cell with built in erasure feature

Methods to improve cell performance in ROM semiconductor integrated circuit devices, in particular split gate cell flash EEPROM devices, without the need for increasing cell size or for decreasing tunnel oxide thickness. The threshold voltage under a first gate electrode (,) is adjusted using a first impurity introducing step, such as an ion implant, and the threshold voltage under a split gate electrode (,) is also adjusted using a second impurity introducing step, such as an ion implant. Depending on the type of cell used, the first gate electrode or the split gate electrode may be used as a floating gate electrode and the threshold voltage under the floating gate electrode may be adjusted separately from the other gate electrode to provide improved cell erase performance, with or without increasing the cell size or decreasing the tunnel oxide thickness.

Method to improve cell performance in split gate flash EEPROM

Dynamic Random Access Memory (DRAM) cells are formed in a P well formed in a biased deep N well (DNW). PMOS transistors are formed in N wells. The NMOS channels stop implant mask is modified not to be a reverse of the N well mask in order to block the channels stop implant from an N+ contact region used for DNW biasing. In DRAMs and other integrated circuits, a minimal spacing requirement between a well of an integrated circuit on the one hand and adjacent circuitry on the other hand is eliminated by laying out the adjacent circuitry so that the well is located adjacent to a transistor having an electrode connected to the same voltage as the voltage that biases the well. For example, in DRAMs, the minimal spacing requirement between the DNW and the read/write circuitry is eliminated by locating the DNW next to a transistor precharging the bit lines before memory accesses. One electrode of the transistor is connected to a precharge voltage. This electrode overlaps the DNW which is biased to the same precharge voltage. This electrode provides the DNW N+ contact region.

Biasing an integrated circuit well with a transistor electrode

A single-poly flash memory cell manufacturable by a standard CMOS fabrication process. A NMOS floating gate (32) is electrically connected to a PMOS floating gate (34). Both gates are fabricated in a single polysilicon process and form a flash memory cell. The floating gates are programmed by Vcc to the source (14) and drain (26) of the NMOS device (28), while applying about -Vcc to the source (20) of the PMOS device (30). Band-to-band hot electrons charge the floating gates. Biasing the NMOS device to operate as a FET allows the charge state of the gate to be sensed from the source current drawn. The memory cell is erased by applying a moderately high voltage to the source (14) NMOS device while negatively biasing the drain (22) of the PMOS device. In a particular embodiment, an integrated circuit device includes a CMOS circuit and a single-poly flash memory circuit. In a further embodiment, a DC-DC on-chip voltage converter produces the erase voltage from conventional CMOS voltage supplies.

Single-poly flash memory cell for embedded application and related

A method of fabricating an E.sup.2 PROM or a flash memory cell having a sharp tip or thin wedge at one of its gates, e.g., the floating gate, for the erasure of electrical charges stored in the floating gate. A recess is formed between a first polysilicon gate and the substrate by removing portions of an insulating layer interposed between the first gate and the substrate. Another insulating layer, e.g., thermal oxide, is formed on the exposed portions of the first gate and the substrate, and partially fills the recess. A second polysilicon layer is formed on the thermal oxide and patterned to form a floating gate. The partially filled recess causes a sharp polysilicon tip or thin wedge to be formed as part of the floating gate. This sharp tip or thin wedge can generate a high electrical field that facilitates the removal of the stored electrical charges from the floating gate.

Growing community of inventors

Taichung, Taiwan

Huoy-Jong Wu