Taiwan Semiconductor Manufacturing Comp. Ltd.

Hung-Wen Su

Chih-Chien Chi

Ya-Lien Lee

Chun-Chieh Lin

Ming-Hsing Tsai

Chen-Yuan Kao

Syun-Ming Jang Jang

Rueijer Lin

Minghsing Tsai

Kai-Shiang Kuo

Shu-Cheng Chin

Pei-Hsuan Lee

Wen-Jiun Liu

Chih-Yi Chang

Chi-Feng Lin

Yao-Min Liu

Szu-Ping Tung

Shih-Wei Chou

Cheng-Hui Weng

Shau-Lin Shue

Yao-Jen Chang

Po-Cheng Shih

Chien-Hsueh Shih

Chia-Pang Kuo

Jun-Yi Ruan

Yu-Hung Lin

Ken-Yu Chang

Yu-Min Chang

Hsiao-Kuan Wei

Hsin-Yun Hsu

Liang-Yueh Ou Yang

Jui-Fen Chien

Kuei-Pin Lee

Ming-Yuan Gao

Hsien-Ming Lee

Chien-An Chen

Sheng-Hsuan Lin

Yen-Chun Lin

Chien Chung Huang

Hung-Chang Hsu

Kuan-Chia Chen

Huei-Wen Hsieh

Nai-Hao Yang

Hsin-Ying Peng

Hsiao-Ping Liu

Cheng-Lun Tsai

Chen-Yi Niu

Yen-Shou Kao

Yung-Cheng Lu

Chih-Hsiang Chang

Ting-Chu Ko

Chun-Sheng Chen

Jen-Chun Wang

Jen-Wei Liu

Wei-Hsiang Chan

Ming-Hsiao Hsieh

Jing-Cheng Lin

Wen-Chih Chiou

Ching-Hua Hsieh

Keng-Chu Lin

Chung-Chi Ko

Tsu Shih

Shing-Chyang Pan

Hui-Lin Chang

Han-Hsin Kuo

Pi-Tsung Chen

Chun-Kai Chang

Wen-Hsuan Chen

Chun Chieh Lin

Ming Hsing Tsai

Hung-Chun Tsai

Huan-yu Shih

Yi-Chi Liao

Ming-Chou Chiang

Wei Hsiang Chan

Mingh-Hsing Tsai

Jui Jen Huang

Kuo-Wei Cheng

A blocking material is selectively deposited on a bottom surface of a back end of line (BEOL) conductive structure such that a barrier layer is selectively deposited on sidewalls of the BEOL conductive structure but not the bottom surface. The blocking material is etched such that copper from a conductive structure underneath is exposed, and a ruthenium layer is deposited on the barrier layer but less ruthenium is deposited on the exposed copper. Accordingly, the barrier layer prevents diffusion of metal ions from the BEOL conductive structure and is substantially absent from the bottom surface as compared to the sidewalls in order to reduce contact resistance. Additionally, the ruthenium layer reduces surface roughness within the BEOL conductive structure and is thinner at the bottom surface as compared to the sidewalls in order to reduce contact resistance.

Conductive structures with bottom-less barriers and liners

A method includes forming a first conductive feature, depositing a graphite layer over the first conductive feature, patterning the graphite layer to form a graphite conductive feature, depositing a dielectric spacer layer on the graphite layer, depositing a first dielectric layer over the dielectric spacer layer, planarizing the first dielectric layer, forming a second dielectric layer over the first dielectric layer, and forming a second conductive feature in the second dielectric layer. The second conductive feature is over and electrically connected to the graphite conductive feature.

Interconnect structure including graphite and method forming same

A method includes forming a first conductive feature in a first dielectric layer. A second dielectric layer is formed over the first conductive feature and the first dielectric layer. An opening is formed in the second dielectric layer. The opening exposes a top surface of the first conductive feature. The top surface of the first conductive feature includes a first metallic material and a second metallic material different from the first metallic material. A native oxide layer is removed from the top surface of the first conductive feature. A surfactant soaking process is performed on the top surface of the first conductive feature. The surfactant soaking process forms a surfactant layer over the top surface of the first conductive feature. A first barrier layer is deposited on a sidewall of the opening. The surfactant layer remains exposed at the end of depositing the first barrier layer.

Interconnect structure of semiconductor device

A structure includes a first conductive feature in a first dielectric layer; a second dielectric layer over the first dielectric layer; and a second conductive feature extending through the second dielectric layer to physically contact the first conductive feature, wherein the second conductive feature includes a metal adhesion layer over and physically contacting the first conductive feature; a barrier layer extending along sidewalls of the second dielectric layer; and a conductive filling material extending over the metal adhesion layer and the barrier layer, wherein a portion of the conductive filling material extends between the barrier layer and the metal adhesion layer.

Via for semiconductor device and method

A semiconductor device includes an insulating layer, wherein the insulating layer has a via opening and a conductive line opening. The semiconductor device further includes a via in the via opening. The semiconductor device further includes a conductive line in the conductive line opening. The conductive line includes a first liner layer, wherein a first thickness of the first liner layer over the via is less than a second thickness of the first liner layer over the insulating layer, and a conductive fill, wherein the first liner layer surrounds the conductive fill.

Semiconductor device having a contact structure

A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.

Method of forming interconnect structure having a barrier layer

A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for weaker and softer dielectric layer. The insert layer may be applied between two weaker dielectric layers or the insert layer may be used with a single layer of dielectric material. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.

Multi-layer film device and method

A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.

Chemical direct pattern plating method

A semiconductor device and method of manufacture are provided which utilize an air gap to help isolate conductive structures within a dielectric layer. A first etch stop layer is deposited over the conductive structures, and the first etch stop layer is patterned to expose corner portions of the conductive structures. A portion of the dielectric layer is removed to form an opening. A second etch stop layer is deposited to line the opening, wherein the second etch stop layer forms a stepped structure over the corner portions of the conductive structures. Dielectric material is then deposited into the opening such that an air gap is formed to isolate the conductive structures.

Method of forming an interconnect structure having an air gap and structure thereof

In some implementations, one or more semiconductor processing tools may form a via within a substrate of a semiconductor device. The one or more semiconductor processing tools may deposit a ruthenium-based liner within the via. The one or more semiconductor processing tools may deposit, after depositing the ruthenium-based liner, a copper plug within the via.

Ruthenium-based liner for a copper interconnect

An opening is formed through a dielectric material layer to physically expose a top surface of a conductive material portion in, or over, a substrate. A metallic nitride liner is formed on a sidewall of the opening and on the top surface of the conductive material portion. A metallic adhesion layer including an alloy of copper and at least one transition metal that is not copper is formed on an inner sidewall of the metallic nitride liner. A copper fill material portion may be formed on an inner sidewall of the metallic adhesion layer. The metallic adhesion layer is thermally stable, and remains free of holes during subsequent thermal processes, which may include reflow of the copper fill material portion. An additional copper fill material portion may be optionally deposited after a reflow process.

Thermally stable copper-alloy adhesion layer for metal interconnect structures and methods for forming the same

A method of making a semiconductor device includes etching an insulating layer to form a first opening and a second opening. The method further includes depositing a conductive material in the first opening. The method further includes performing a surface modification process on the conductive material. The method further includes depositing, after the surface modification process, a first liner layer in the second opening, wherein the first liner layer extends over the conductive material and the insulating layer. The method further includes depositing a conductive fill over the first liner layer, wherein the conductive fill includes a different material from the conductive material.

Method of making a contact structure

An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a conductive plug over a substrate; a conductive feature over the conductive plug, wherein the conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a bottom surface; and a carbon-containing barrier layer having a first portion along the first sidewall of the conductive feature, a second portion along the second sidewall of the conductive feature, and a third portion along the bottom surface of the conductive feature.

Interconnect structure having a carbon-containing barrier layer

A semiconductor device is manufactured by modifying an electromagnetic field within a deposition chamber. In embodiments in which the deposition process is a sputtering process, the electromagnetic field may be modified by adjusting a distance between a first coil and a mounting platform. In other embodiments, the electromagnetic field may be adjusted by applying or removing power from additional coils that are also present.

Semiconductor device, method and machine of manufacture

Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.

Selective capping processes and structures formed thereby

Growing community of inventors

Jhubei, Taiwan

Hung-Wen Su