Chipmos Technologies Inc.

Chipmos Technologies (Bermuda) Ltd

Hung Tsun Lin

Geng-Shin Shen

Yu-Ren Chen

Cheng Ting Wu

Wu Chang Tu

An IC package primarily includes a chip, a plurality of electrical connecting components, and a chip carrier including a substrate, a die-attaching layer, and at least one bonding wire. The substrate has a top surface and a bottom surface wherein the top surface includes a die-attaching area for being disposed with the die-attaching layer. The chip is attached to the die-attaching area by the die-attaching layer and is electrically connected to the substrate by the electrical connecting components. Both ends of the bonding wire are bonded respectively to two interconnecting fingers on the top surface of the substrate, and at least a portion of the bonding wire is encapsulated in the die-attaching layer such that some wirings or vias formed on a conventional substrate are not needed. Therefore, the substrate can have a simpler structure and fewer numbers of wiring layers; consequently, the substrate cost can be reduced.

IC package reducing wiring layers on substrate and its carrier

A stacked package structure with leadframe having bus bar, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, in which the die pad is provided between the inner leads and is vertically distant from the inner leads; a bus bar being provided between the inner leads and the die pad; an offset chip-stacked structure stacked by a plurality of chips, the offset chip-stacked structure being fixedly connected to a first surface of the die pad and electrically connected to the inner leads; and an encapsulant covering the offset chip-stacked structure, the inner leads, the first surface of die pad, and the upper surface of bus bar, the second surface of die pad and the lower surface of bus bar being exposed and the outer leads extending out of the encapsulant.

Stacked chip packaging with heat sink structure

The present invention provides a package structure with lead-frame on stacked chips, comprising: a lead-frame, composed of a plurality of outer leads arranged in rows facing each other and a plurality of inner leads arranged in rows facing each other formed by a plurality of wires, wherein the plurality of inner leads are divided into first inner leads and second inner leads, and the length of the first inner leads is greater than that of the second inner leads; and a plurality of semiconductor chip devices. The active surface of each chip faces upward and chips are misaligned to form offset stacked structure, wherein the semiconductor chip device stacked uppermost is fixedly connected under said first inner leads, and the plurality of semiconductor chip devices are electrically connected to the first inner leads and the second inner leads on the same side edge.

Package structure with leadframe on offset chip-stacked structure

A chip package structure includes a circuit substrate, a chip, an adhesive layer, conductive wires, and a molding compound. The circuit substrate has a first, a second surface, a slot, and a solder mask layer disposed on the first surface. The solder mask layer has a first and a second opening located at two sides of a longitude direction of the slot. The chip is disposed on the first surface and covers at least a portion of the slot. The adhesive layer is disposed between the chip and the circuit substrate and located at two sides of each of the slot, the first opening, and the second opening. The conductive wires connect the chip and the second surface through the slot. The molding compound covers the chip, the adhesive layer, and the conductive wires and the molding compound is further filling into the slot, the first and the second opening.

Growing community of inventors

Hsinchu, Taiwan

Hung Tsun Lin