Samsung Electronics Co., Ltd.

Hung-Mo Yang

Keun-Nam Kim

Choong-Ho Lee

Myoung-Seob Shim

A fin field effect transistor (fin FET) is formed using a bulk silicon substrate and sufficiently guarantees a top channel length formed under a gate, by forming a recess having a predetermined depth in a fin active region and then by forming the gate in an upper part of the recess. A device isolation film is formed to define a non-active region and a fin active region in a predetermined region of the substrate. In a portion of the device isolation film a first recess is formed, and in a portion of the fin active region a second recess having a depth shallower than the first recess is formed. A gate insulation layer is formed within the second recess, and a gate is formed in an upper part of the second recess. A source/drain region is formed in the fin active region of both sides of a gate electrode.

Fin FET and method of fabricating same

fin FET and method of fabricating same

A method of fabricating a 3D field effect transistor employing a hard mask spacer includes forming a hard mask pattern on a semiconductor substrate. The semiconductor substrate is etched using the hard mask pattern as an etch mask to form a trench that defines an active region. A trench oxide layer and a liner are sequentially formed on the semiconductor substrate, and an isolation layer is formed to fill the trench. An upper surface of the isolation layer may by recessed below an upper surface of the hard mask pattern. A hard mask spacer is formed that covers sidewalls of the hard mask pattern. Some portions of the isolation layer where an etching is blocked by the hard mask spacer remain on sidewalls of the channel region, respectively, thereby preventing the liner from being damaged by etching.

Method of fabricating a three-dimensional MOSFET employing a hard mask spacer

A wafer that is less susceptible to chipping or peeling during a sawing process is disclosed. The wafer includes a plurality of chips, scribe lanes formed between the plurality of chips, and a passivation film, which is formed on the plurality of chips and the scribe lanes and has a plurality of perforations, e.g. slit patterns engraved on each scribe lane. A photolithography reticle and method of manufacturing the wafer are also provided.

Wafer having scribe lanes suitable for sawing process, reticle used in manufacturing the same, and method of manufacturing the same

A storage electrode structure and method of manufacturing thereof. Storage electrodes of dummy cells arranged in a word line direction and a bit line direction at the peripheral regions of a cell are formed such that every two or three dummy cells in a word line direction are formed in a single pattern. As a result, the loading effect produced in the peripheral regions of the cell region is reduced. The invention also reduces short-circuit bridging caused by collapsing storage electrode patterns in the dummy cells since the storage electrodes are not connected together. Accordingly, it is possible to minimize an increase in the loading capacitance of bit lines when an electrical short circuit occurs between a bit line and an associated buried contact.

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Gyeonggi-do, South Korea

Hung-Mo Yang