Hewlett-packard Company

Actel Corporation, Inc.

Other

Applied Materials, Inc.

Hung-Kwei Hu

Yeouchung Yen

Shih-Oh Chen

Meihua Shen

Warren M Uesato

Paul K Aum

Jianping Wen

Kwang-Leei K Young

In a method of etching a substrate, a substrate is provided in a process zone, the substrate having a pattern of features comprising dielectric covering semiconductor. In a first stage, an energized first etching gas is provided in the process zone, the energized first etching gas having a first selectivity of etching dielectric to semiconductor of at least about 1.8:1, wherein the dielectric is etched preferentially to the semiconductor to etch through the dielectric to at least partially expose the semiconductor. In a second stage, an energized second etching gas is provided in the process zone, the energized second etching gas having a second selectivity of etching dielectric to semiconductor of less than about 1:1.8, wherein the semiconductor is etched preferentially to the dielectric.

Method of etching shaped features on a substrate

Methods for use in fabricating integrated circuit structures. One embodiment of the present invention is a quasi-damascene gate, self-aligned source/drain method for forming a device on a substrate that includes steps of: (a) forming a gate dielectric layer over the substrate; (b) forming a first gate electrode layer over the gate dielectric layer; (c) forming a contact etch stop layer over the first gate electrode layer; (d) forming a self-aligning layer over the contact etch stop layer; and (e) forming and patterning a mask over the self-aligning layer.

Quasi-damascene gate, self-aligned source/drain methods for fabricating devices

A method for fabricating the antifuse of the present invention comprises the steps of forming a lower antifuse electrode; forming a relatively thick interlayer dielectric layer over the surface of the lower antifuse electrode; forming a masking layer, preferably a photoresist, including an aperture therein having a first area over the interlayer dielectric layer; performing a first vertical etching step on the interlayer dielectric layer to a first selected depth; enlarging the aperture in the masking layer until it has a second area; performing a final vertical etching step on the interlayer dielectric layer to expose the upper surface of the lower electrode. Depending on the thickness of the interlayer dielectric, additional enlarging steps and vertical etching steps may be performed prior to the final vertical etching step which exposes the upper surface of the lower electrode. An aperture having a staircase profile is thereby formed, the aperture having a number of steps thus reducing and/or eliminating cusping and/or thinning at the corner and bottom of the antifuse cell opening allowing for the uniform deposit of dielectric and upper antifuse electrode materials.

Method for fabricating an electrically programmable antifuse

An antifuse comprises a lower electrode and an upper electrode separated by an interlayer dielectric. An antifuse cell opening is disposed in the interlayer dielectric. The antifuse cell opening comprises at least two steps, wherein a first portion thereof has a first area and a second portion thereof disposed above the first portion has a second area larger than said first area. Additional portions may be provided above the second portion having successively larger areas if the thickness of the interlayer dielectric warrants their inclusion.

Electrically programmable antifuse having stair aperture

During the manufacture of a semiconductor integrated circuit, contact holes or passages are formed through a non-planar insulating layer resulting from the deposition of dielectric over electrical contacts having differing profile heights from the surface of an internal layer, such as a substrate, to expose these contacts and/or provide electrical connections thereto. The passages are formed with a combination of sloped and vertical sidewall portions in which varying depth sloped portions are used to effectively planarize the dielectric layer and permit the vertical sidewall portions to have substantially identical vertical dimensions. This technique simultaneously exposes contacts with varying profile heights which thereby reduces contact damage. In addition, this technique effectively planarizes the dielectric layer, reducing the need for an additional planarization step.

Simultaneous dielectric planarization and contact hole etching

A controllable feature shrinkage technique permits shrinkage of feature sizes beyond the capability of current lithographic tools by using high temperature flow to shrink the conventionally formed resist image of the feature and then deep UV exposure to stabilize the resist profile at the desired reduced size. A preliminary partial stabilization using hard bake and low intensity deep UV exposure reduces the rate of resist flow at temperature, permitting better control and repeatability of the amount of shrinkage. Feature sizes in the range of about 0.15 .mu.m may be achieved.

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Saratoga, CA, United States of America

Hung-Kwei Hu