Taiwan Semiconductor Manufacturing Comp. Ltd.

Parabellum Strategic Opportunities Fund LLC

Hung-Jui Kuo

Yu-Hsiang Hu

Chen-Hua Douglas Yu

Sih-Hao Liao

Hui-Jung Tsai

Chung-Shi Liu

Ming-Che Ho

Po-Han Wang

Wei-Chih Chen

Zi-Jheng Liu

Yi-Wen Wu

Ming-Tan Lee

Yung-Chi Chu

Yun Chen Hsieh

Tzung-Hui Lee

Jyun-Siang Peng

Chen-Cheng Kuo

Hung-Chun Cho

Tai-Min Chang

Jhih-Yu Wang

Ming-Da Cheng

Yi-Yang Lei

Meng-Che Tu

Mirng-Ji Lii

Kai-Chiang Wu

Chia-Wei Wang

Yu-Feng Chen

Jo-Lin Lan

Shih-Hao Tseng

Tian Hu

Hsien-Wei Chen

Wei-Yu Chen

Wei-Hung Lin

Chien Ling Hwang

Meng-Wei Chou

De-Yuan Lu

Keng-Han Lin

Ting-Chen Tseng

Yu Yi Huang

Der-Chyang Yeh

Han-Ping Pu

Chun-Lin Lu

Tuan-Yu Hung

Hao-Yi Tsai

Chih Hsuan Wang

Yu-Tzu Chang

Jing-Cheng Lin

Alexander Kalnitsky

An-Jhih Su

Chi-Hsi Wu

Chun-Chieh Wang

Chih-Hua Chen

Chin-Yu Ku

Ching-Feng Yang

Chia-Hung Liu

Ting-Chu Ko

Ming Shih Yeh

Ching-Wen Chen

Shih-Peng Tai

Ching-Hui Chen

Hsien-Liang Meng

Chien Rhone Wang

Chih-Wei Lai

Tzong-Hann Yang

Wei-Chung Chang

Shin-Puu Jeng

Chih-Wei Lin

Chien-Hsun Lee

Li-Hsien Huang

Tsung-Ding Wang

Kuo-Chio Liu

Jaw-Jung Shin

Yu-min Liang

Hao-Cheng Hou

Jung-Wei Cheng

Yu-Ren Chen

Ching-Yu Chang

Chin-Hsiang Lin

Shinn-Sheng Yu

Wen-Hsiung Lu

Tsung-Shu Lin

Chun-Hung Lin

Hsin-Yu Pan

Hua-Tai Lin

Kuei Shun Chen

Chi-Ming Tsai

Po-Yuan Teng

Heng-Jen Lee

Kuo-Lung Pan

Ko-Bin Kao

Shu-Rong Chun

Li-Kong Turn

Bang-Chein Ho

Tsung-Chih Chien

Mao-Yen Chang

Yu-Ming Lee

Yu-Ling Tsai

Wei-Kang Hsieh

An integrated fan-out (InFO) package includes a die, an encapsulant laterally encapsulating the die, and a redistribution structure. The redistribution structure is disposed on the encapsulant. The redistribution structure includes a plurality of routing patterns and a plurality of alignment marks. The routing patterns are electrically connected to the die. The alignment marks surround the routing patterns. The alignment marks are electrically insulated from the die and the routing patterns. At least one of the alignment marks is in physical contact with the encapsulant, and the alignment marks located at different level heights are arranged in a non-overlapping manner vertically.

Integrated fan-out package and manufacturing method thereof

A package structure includes a semiconductor die, conductive pillars, an insulating encapsulation, a redistribution circuit structure, and a solder resist layer. The conductive pillars are arranged aside of the semiconductor die. The insulating encapsulation encapsulates the semiconductor die and the conductive pillars, and the insulating encapsulation has a first surface and a second surface opposite to the first surface. The redistribution circuit structure is located on the first surface of the insulating encapsulation. The solder resist layer is located on the second surface of the insulating encapsulation, wherein a material of the solder resist layer includes a filler.

Package structure and method of manufacturing the same

A passivation layer and conductive via are provided, wherein the transmittance of an imaging energy is increased within the material of the passivation layer. The increase in transmittance allows for a greater cross-linking that helps to increase control over the contours of openings formed within the passivation layer. Once the openings are formed, the conductive vias can be formed within the openings.

Methods of manufacture having redistribution layer using dielectric material photoactive component

In an embodiment, a device includes: a semiconductor die including a semiconductor material; a through via adjacent the semiconductor die, the through via including a metal; an encapsulant around the through via and the semiconductor die, the encapsulant including a polymer resin; and an adhesion layer between the encapsulant and the through via, the adhesion layer including an adhesive compound having an aromatic compound and an amino group, the amino group bonded to the polymer resin of the encapsulant, the aromatic compound bonded to the metal of the through via, the aromatic compound being chemically inert to the semiconductor material of the semiconductor die.

Integrated circuit packages having adhesion layers for through vias

A semiconductor device having a redistribution structure and a method of forming the same are provided. A semiconductor device includes a semiconductor structure, a redistribution structure over and electrically coupled the semiconductor structure, and a connector over and electrically coupled to the redistribution structure. The redistribution structure includes a base via and stacked vias electrically interposed between the base via and the connector. The stacked vias are laterally spaced apart from the base via.

Redistribution structure for semiconductor device and method of forming same

A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region.

Semiconductor structure having a conductive feature comprising an adhesion layer and a metal region over and contacting the adhesion layer

A semiconductor device includes semiconductor dies and a redistribution structure. The semiconductor dies are encapsulated in an encapsulant. The redistribution structure extends on the encapsulant and electrically connects the semiconductor dies. The redistribution structure includes dielectric layers and redistribution conductive layers alternately stacked. An outermost dielectric layer of the dielectric layers further away from the semiconductor dies is made of a first material. A first dielectric layer of the dielectric layers on which the outermost dielectric layer extends is made of a second material different from the first material. The first material includes at least one material selected from the group consisting of an epoxy resin, a phenolic resin, a polybenzooxazole, and a polyimide having a curing temperature lower than 250° C.

Semiconductor device and manufacturing method thereof

A method of fabricating an integrated fan-out package is provided. The method includes the following steps. An integrated circuit component is provided on a substrate. An insulating encapsulation is formed on the substrate to encapsulate sidewalls of the integrated circuit component. A redistribution circuit structure is formed along a build-up direction on the integrated circuit component and the insulating encapsulation. The formation of the redistribution circuit structure includes the following steps. A dielectric layer and a plurality of conductive vias embedded in the dielectric layer are formed, wherein a lateral dimension of each of the conductive vias decreases along the build-up direction. A plurality of conductive wirings is formed on the plurality of conductive vias and the dielectric layer. An integrated fan-out package of the same is also provided.

Package structure

A photoresist apparatus and a method are provided. The photoresist apparatus includes a pre-baking apparatus. The pre-baking apparatus includes: a hot-plate, a first cover over the hot-plate, a second cover over the first cover, a first heating element extending along a topmost surface of the first cover, and a second heating element extending along a topmost surface of the second cover.

Photoresist system and method

In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die; and a redistribution structure including: a plurality of dielectric layers over the encapsulant and the integrated circuit die; a plurality of metallization patterns in the dielectric layers, the metallization patterns being electrically coupled to the integrated circuit die; and a sealing ring in the dielectric layers, the sealing ring extending around the metallization patterns, the sealing ring being electrically isolated from the metallization patterns and the integrated circuit die, the sealing ring including a plurality of sealing ring layers, each of the sealing ring layers including a via portion extending through a respective one of the dielectric layers, the via portion of each of the sealing ring layers being aligned along a same common axis.

Integrated circuit package and method

A semiconductor package including a plurality of semiconductor devices, an insulating layer, and a redistribution layer is provided. The insulating layer is disposed over the semiconductor device. The redistribution layer is disposed over the insulating layer and electrically connected to the semiconductor device. The redistribution layer includes a conductive line portion. The semiconductor package has a stitching zone, and the insulating layer has a ridge structure on a surface away from the semiconductor device and positioned within the stitching zone.

Semiconductor package and method for manufacturing the same

A manufacturing method of a semiconductor package includes the following steps. An integrated circuit structure is provided, wherein the integrated circuit structure includes an integrated circuit and a metallization layer covering a back surface of the integrated circuit. An encapsulation material is provided to laterally encapsulate the integrated circuit structure. A redistribution structure is provided over the integrated circuit structure and the encapsulation material, wherein the redistribution structure includes a thermal metal layer furthermost from the integrated circuit structure, wherein the thermal metal layer is thermally coupled to the metallization layer. A solder layer is provided over the thermal metal layer, wherein the solder layer is thermally coupled to the thermal metal layer.

Manufacturing method of semiconductor package

A semiconductor device including a semiconductor die, an encapsulant and a redistribution structure is provided. The encapsulant laterally encapsulates the semiconductor die. The redistribution structure is disposed on the semiconductor die and the encapsulant and is electrically connected to the semiconductor die. The redistribution structure includes a dielectric layer, a conductive via in the dielectric layer and a redistribution wiring covering the conductive via and a portion of the dielectric layer. The conductive via includes a pillar portion embedded in the dielectric layer and a protruding portion protruding from the pillar portion, wherein the protruding portion has a tapered sidewall.

Semiconductor device and method of fabricating the same

A package structure includes a first redistribution layer, a semiconductor die and a second redistribution layer. The first redistribution layer includes a first dielectric layer, first conductive elements, second conductive elements, a top dielectric layer and an auxiliary dielectric portion. The first conductive elements and the second conductive elements are disposed on the first dielectric layer with a first pattern density and a second pattern density respectively. The top dielectric layer is disposed on the first dielectric layer and covering a top surface of the second conductive elements. The auxiliary dielectric portion is disposed in between the first dielectric layer and the top dielectric layer, and covering a top surface of the first conductive elements. The semiconductor die is disposed on the first redistribution layer. The second redistribution layer is disposed on the semiconductor die, and electrically connected to the semiconductor die and the first redistribution layer.

Package structure including auxiliary dielectric portion

A semiconductor package includes a substrate, a composite seed-barrier layer, a routing via, and a semiconductor die. The substrate has a through hole formed therethrough. The composite seed-barrier layer extends on sidewalls of the through hole and includes a first barrier layer, a seed layer, and a second barrier layer sequentially stacked on the sidewalls of the through hole. The routing via fills the through hole and is separated from the substrate by the composite seed-barrier layer. The semiconductor die is electrically connected to the routing via. Along the sidewalls of the through holes, at a level height corresponding to half of a total thickness of the substrate, the seed layer is present as inclusions of seed material surrounded by barrier material of the first barrier layer and the second barrier layer.

Semiconductor package having composite seed-barrier layer and method of forming the same

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Hsinchu, Taiwan

Hung-Jui Kuo