Taiwan Semiconductor Manufacturing Comp. Ltd.

Parabellum Strategic Opportunities Fund LLC

Hung-Jui Kuo

Yu-Hsiang Hu

Chen-Hua Douglas Yu

Sih-Hao Liao

Hui-Jung Tsai

Chung-Shi Liu

Ming-Che Ho

Po-Han Wang

Wei-Chih Chen

Zi-Jheng Liu

Yi-Wen Wu

Ming-Tan Lee

Yung-Chi Chu

Yun Chen Hsieh

Tzung-Hui Lee

Tai-Min Chang

Jyun-Siang Peng

Chen-Cheng Kuo

Hung-Chun Cho

Jhih-Yu Wang

Ming-Da Cheng

Chia-Wei Wang

Yi-Yang Lei

Meng-Che Tu

Mirng-Ji Lii

Kai-Chiang Wu

Jo-Lin Lan

Ting-Chen Tseng

Shih-Hao Tseng

Tian Hu

Yu-Feng Chen

De-Yuan Lu

Hsien-Wei Chen

Wei-Yu Chen

Wei-Hung Lin

Chien Ling Hwang

Meng-Wei Chou

Keng-Han Lin

Yu Yi Huang

Der-Chyang Yeh

Han-Ping Pu

Chun-Lin Lu

Tuan-Yu Hung

Hao-Yi Tsai

Chih Hsuan Wang

Yu-Tzu Chang

Jing-Cheng Lin

Alexander Kalnitsky

An-Jhih Su

Chi-Hsi Wu

Chun-Chieh Wang

Chih-Hua Chen

Chin-Yu Ku

Ching-Feng Yang

Chia-Hung Liu

Ting-Chu Ko

Ming Shih Yeh

Ching-Wen Chen

Shih-Peng Tai

Ching-Hui Chen

Hsien-Liang Meng

Chien Rhone Wang

Chih-Wei Lai

Tzong-Hann Yang

Wei-Chung Chang

Shin-Puu Jeng

Chih-Wei Lin

Chien-Hsun Lee

Li-Hsien Huang

Tsung-Ding Wang

Kuo-Chio Liu

Jaw-Jung Shin

Yu-min Liang

Hao-Cheng Hou

Jung-Wei Cheng

Yu-Ren Chen

Ching-Yu Chang

Chin-Hsiang Lin

Shinn-Sheng Yu

Wen-Hsiung Lu

Tsung-Shu Lin

Chun-Hung Lin

Yu-Chia Lai

Hsin-Yu Pan

Hua-Tai Lin

Kuei Shun Chen

Chi-Ming Tsai

Po-Yuan Teng

Heng-Jen Lee

Kuo-Lung Pan

Ko-Bin Kao

Shu-Rong Chun

Li-Kong Turn

Bang-Chein Ho

Mao-Yen Chang

Tsung-Chih Chien

Yu-Ming Lee

Yu-Ling Tsai

Wei-Kang Hsieh

A semiconductor structure includes a semiconductor die, a redistribution circuit structure, and a terminal. The redistribution circuit structure is disposed on and electrically coupled to the semiconductor die. The terminal is disposed on and electrically coupled to the redistribution circuit structure, where the redistribution circuit structure is disposed between the semiconductor die and the terminal, and the terminal includes an under-bump metallization (UBM) and a capping layer. The UBM is disposed on and electrically coupled to the redistribution circuit structure, where the UBM includes a recess. The capping layer is disposed on and electrically coupled to the UBM, where the UBM is between the capping layer and the redistribution circuit structure, and the capping layer fills the recess of the UBM.

Semiconductor structure, stacked structure with terminal comprising capping layer and manufacturing method thereof

A manufacturing method of a semiconductor package includes: laterally covering a sensing die with an encapsulant, where the encapsulant includes a top surface and a rounded inner edge connected to the top surface, and a top surface of the sensing die is lower than the rounded inner edge of the encapsulant and is smoother than the top surface of the encapsulant; and forming a redistribution structure on the top surface of the encapsulant and the top surface of the sensing die.

Fabricating a sensing component encapsulated by an encapsulation layer with roughed surface having a hollow region

In an embodiment, a method includes: dispensing a first dielectric layer around and on a first metallization pattern, the first dielectric layer including a photoinsensitive molding compound; planarizing the first dielectric layer such that surfaces of the first dielectric layer and the first metallization pattern are planar; forming a second metallization pattern on the first dielectric layer and the first metallization pattern; dispensing a second dielectric layer around the second metallization pattern and on the first dielectric layer, the second dielectric layer including a photosensitive molding compound; patterning the second dielectric layer with openings exposing portions of the second metallization pattern; and forming a third metallization pattern on the second dielectric layer and in the openings extending through the second dielectric layer, the third metallization pattern coupled to the portions of the second metallization pattern exposed by the openings.

Integrated circuit package and method

A semiconductor package includes a first integrated circuit, a first passivation layer, a second passivation layer, a thermal pattern, an adhesive layer and a second integrated circuit. The first integrated circuit is encapsulated by an encapsulant. The first passivation layer is disposed over the first integrated circuit and the encapsulant. The second passivation layer is disposed over the first passivation layer. The thermal pattern is disposed in the first passivation layer and the second passivation layer. The adhesive layer is disposed over the second passivation layer and in direct contact with the thermal pattern. The second integrated circuit is adhered to the first integrated circuit through the adhesive layer.

Semiconductor packages and method of manufacturing the same

A method embodiment includes forming a patterned first photo resist over a seed layer. A first opening in the patterned first photo resist exposes the seed layer. The method further includes plating a first conductive material in the first opening on the seed layer, removing the patterned first photo resist, and after removing the patterned first photo resist, forming a patterned second photo resist over the first conductive material. A second opening in the patterned second photo resist exposes a portion of the first conductive material. The method further includes plating a second conductive material in the second opening on the first conductive material, removing the patterned second photo resist, and after removing the patterned second photo resist, depositing a dielectric layer around the first conductive material and the second conductive material.

Dense redistribution layers in semiconductor packages and methods of forming the same

Provided is a package structure including a first die and an encapsulant. The first die includes a substrate, a plurality of pads over the substrate, a passivation layer on portions of each of the plurality of pads, a plurality of first die connectors on the plurality of pads, respectively and a dielectric layer laterally encapsulating the plurality of first die connectors. The encapsulant laterally encapsulates the first die. One of the plurality of first die connectors is a taper-shaped die connector. A width of the one of the plurality of first die connectors gradually increases from a top surface of the one of the plurality of first die connectors toward the a top surface of the passivation layer.

Package structure including a die having a taper-shaped die connector

A device includes a molding compound, a plurality of through vias, a seal ring structure, and a protection layer. The plurality of through vias are embedded in the molding compound. The seal ring structure is over the molding compound and surrounds the through vias in a top view. The protection layer covers the seal ring and extends toward the molding compound in a cross-sectional view.

Semiconductor device

A semiconductor package including a semiconductor die, an encapsulant, an electrical connector, a conductive pad and an inter-dielectric layer is provided. The encapsulant encapsulates the semiconductor die. The electrical connector is disposed over the semiconductor die. The conductive pad contacts the electrical connector and is disposed between the semiconductor die and the electrical connector. The inter-dielectric layer is disposed over the semiconductor die, wherein the inter-dielectric layer comprises an opening, and a portion of the opening is occupied by the conductive pad and the electrical connector.

Semiconductor package

A package includes a device die, an encapsulant encapsulating the device die therein, a first plurality of through-vias penetrating through the encapsulant, a second plurality of through-vias penetrating through the encapsulant, and redistribution lines over and electrically coupling to the first plurality of through-vias. The first plurality of through-vias include an array. The second plurality of through-vias are outside of the first array, and the second plurality of through-vias are larger than the first plurality of through-vias.

Packages with enlarged through-vias in encapsulant

An apparatus and a method for effectively exhausting evaporated material are provided. In an embodiment the apparatus includes a hot plate and an exhaust hood assembly suspended over the hot plate. The exhaust hood assembly includes a trench plate, a cover plate over the trench plate and a single exhaust pipe header over and attached to a single exhaust opening of the cover plate. During operation, the exhaust hood assembly reduces the amount of condensation and also collects any remaining condensation in order to help prevent condensation from impacting further manufacturing steps.

Apparatus, system and method

An integrated fan-out (InFO) package includes a die, an encapsulant laterally encapsulating the die, and a redistribution structure. The redistribution structure is disposed on the encapsulant. The redistribution structure includes a plurality of routing patterns and a plurality of alignment marks. The routing patterns are electrically connected to the die. The alignment marks surround the routing patterns. The alignment marks are electrically insulated from the die and the routing patterns. At least one of the alignment marks is in physical contact with the encapsulant, and the alignment marks located at different level heights are arranged in a non-overlapping manner vertically.

Integrated fan-out package and manufacturing method thereof

A package structure includes a semiconductor die, conductive pillars, an insulating encapsulation, a redistribution circuit structure, and a solder resist layer. The conductive pillars are arranged aside of the semiconductor die. The insulating encapsulation encapsulates the semiconductor die and the conductive pillars, and the insulating encapsulation has a first surface and a second surface opposite to the first surface. The redistribution circuit structure is located on the first surface of the insulating encapsulation. The solder resist layer is located on the second surface of the insulating encapsulation, wherein a material of the solder resist layer includes a filler.

Package structure and method of manufacturing the same

A passivation layer and conductive via are provided, wherein the transmittance of an imaging energy is increased within the material of the passivation layer. The increase in transmittance allows for a greater cross-linking that helps to increase control over the contours of openings formed within the passivation layer. Once the openings are formed, the conductive vias can be formed within the openings.

Methods of manufacture having redistribution layer using dielectric material photoactive component

In an embodiment, a device includes: a semiconductor die including a semiconductor material; a through via adjacent the semiconductor die, the through via including a metal; an encapsulant around the through via and the semiconductor die, the encapsulant including a polymer resin; and an adhesion layer between the encapsulant and the through via, the adhesion layer including an adhesive compound having an aromatic compound and an amino group, the amino group bonded to the polymer resin of the encapsulant, the aromatic compound bonded to the metal of the through via, the aromatic compound being chemically inert to the semiconductor material of the semiconductor die.

Integrated circuit packages having adhesion layers for through vias

A semiconductor device having a redistribution structure and a method of forming the same are provided. A semiconductor device includes a semiconductor structure, a redistribution structure over and electrically coupled the semiconductor structure, and a connector over and electrically coupled to the redistribution structure. The redistribution structure includes a base via and stacked vias electrically interposed between the base via and the connector. The stacked vias are laterally spaced apart from the base via.

Redistribution structure for semiconductor device and method of forming same

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Hsinchu, Taiwan

Hung-Jui Kuo