Taiwan Semiconductor Manufacturing Comp. Ltd.

Hung Jui Chang

Yi-Wei Chiu

Chia-Ching Tsai

Yu-Wei Kuo

Li-Te Hsu

Yu-Chi Lin

Chin-Hsing Lin

You-Hua Chou

Bo-Jhih Shen

Yu Lun Ke

Allen Ke

Ying-Lang Wang

Chih-Tsung Lee

Horng-Huei Tseng

Kei-Wei Chen

Shiu-Ko JangJian

Chih-Hao Chen

Yu-Ku Lin

Sheng-Wen Chen

Chung-En Kao

Chin Kun Lan

Ming-Chin Tsai

Hsiang Hsiang Ko

Te-Ming Kung

Chung-Bin Tseng

Jeng Chang Her

Ming-Shiou Kuo

Li Te Hsu

Yu-Lun Ke

Huan-Wen Lai

Shiu-Ko Jang Jian

Yu-Li Hung

Hsien-Wei Lin

Yi Ming Chen

Chia-Kai Sun

A dielectric layer is formed over a substrate, an anti-reflective layer is formed over the dielectric layer, and a first hardmask is formed over the anti-reflective layer. A via opening and a trench opening are formed within the dielectric layer using the anti-reflective layer and the first hardmask as masking materials. After the formation of the trench opening and the via opening, the first hardmask is removed. An interconnect is formed within the openings, and the interconnect has a via with a profile angle of between about 70° and about 80° and a depth ratio of between about 65% and about 70%.

Semiconductor device and method of manufacture

Implementations of the present disclosure provide methods for preventing contact damage or oxidation after via/trench opening formation. In one example, the method includes forming an opening in a structure on the substrate to expose a portion of a surface of an electrically conductive feature, and bombarding a surface of a mask layer of the structure using energy species formed from a plasma to release reactive species from the mask layer, wherein the released reactive species form a barrier layer on the exposed surface of the electrically conductive feature.

Method of forming a barrier layer in an interconnect structure of semiconductor device

A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.

Etch profile control of interconnect structures

A dielectric layer is formed over a substrate, an anti-reflective layer is formed over the dielectric layer, and a first hardmask is formed over the anti-reflective layer. A via opening and a trench opening are formed within the dielectric layer using the anti-reflective layer and the first hardmask as masking materials. After the formation of the trench opening and the via opening, the first hardmask is removed. An interconnect is formed within the openings, and the interconnect has a via with a profile angle of between about 70&#xb0; and about 80&#xb0; and a depth ratio of between about 65% and about 70%.

Interconnect structure of semiconductor device including barrier layer located entirely in via

A method includes mounting a wafer on a chuck disposed within a chamber of an etching system, the wafer being encircled by a focus ring. While etching portions of the wafer, an etch direction is adjusted to a first desired etch direction by adjusting a vertical position of the focus ring relative to the wafer to a first desired vertical position. While etching portions of the wafer, the etch direction is adjusted to a second desired etch direction by adjusting the vertical position of the focus ring relative to the wafer to a second desired vertical position. The second desired vertical position is different from the first desired vertical position. The second desired etch direction is different from the first desired etch direction.

Focus ring for plasma etcher

The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having reduced trench loading effect. The present disclosure provides a novel multi-layer cap film incorporating one or more oxygen-based layers for reducing trench loading effects in semiconductor devices. The multi-layer cap film can be made of a metal hard mask layer and one or more oxygen-based layers. The metal hard mask layer can be formed of titanium nitride (TiN). The oxygen-based layer can be formed of tetraethyl orthosilicate (TEOS).

Semiconductor device with reduced trench loading effect

An interconnect structure and a method of forming are provided. The method includes forming an opening in a dielectric layer and an etch stop layer, wherein the opening extends only partially through the etch stop layer. The method also includes creating a vacuum environment around the device. After creating the vacuum environment around the device, the method includes etching through the etch stop layer to extend the opening and expose a first conductive feature. The method also includes forming a second conductive feature in the opening.

Methods of forming conductive features using a vacuum environment

A semiconductor manufacturing method and semiconductor manufacturing tool for performing the same are disclosed. The semiconductor manufacturing tool includes a plasma chamber, a mounting platform disposed within the plasma chamber, a focus ring disposed within the plasma chamber, and at least one actuator mechanically coupled to the focus ring and configured to move the focus ring vertically. The actuator is configured to move the focus ring vertically when a plasma is present in the plasma chamber.

Moving focus ring for plasma etcher

Methods of forming interconnect structures using a vacuum environment

Post-etch treatment of an electrically conductive feature

Growing community of inventors

Shetou Shiang, Taiwan

Hung Jui Chang