Taiwan Semiconductor Manufacturing Comp. Ltd.

Hung-Jen Lin

Tsung-Ding Wang

Chien-Hsun Lee

Hao-Cheng Hou

Jung Wei Cheng

Chung-Shi Liu

Wen-Hsiung Lu

Chien-Hsiun Lee

Ming-Che Liu

Chun-Chih Chuang

Ming-Da Cheng

Kai-Chiang Wu

Jiun Yi Wu

Chun-Lin Lu

Shih-Wei Liang

Yen-Ping Wang

Ming-Kai Liu

Ching-Feng Yang

Chia-Chun Miao

Hai-Ming Chen

Hsien-Wei Chen

Mirng-Ji Lii

Tsung-Yuan Yu

Yu-min Liang

Jung-Wei Cheng

Li-Wei Chou

Chen-Hua Douglas Yu

Ching-Hwanq Su

Chen-Ming Huang

Chih-Mu Huang

Min-Hwa Chi

Chih-Heng Shen

Chih-Fu Chang

Ching-Chen Hao

Yen-Hsiu Chen

Ming-Chu King

Yun Chen Chang

Li-Chuen Cheng

Chih-Chen Ku

San-Sun Yang

A semiconductor package includes a first integrated circuit, a first conductive via, a second conductive via, a second integrated circuit, a third conductive via and an encapsulant. The first conductive via is disposed in a first passivation layer over the first integrated circuit. The second conductive via is disposed in a second passivation layer over the first passivation layer. The second conductive via is electrically connected to the first conductive via. The third conductive via is disposed over the second integrated circuit, wherein a surface of the third conductive via is substantially coplanar with a surface of the third conductive via. The encapsulant encapsulates the first integrated circuit, the first passivation layer, the second passivation layer, the second integrated circuit and the third conductive via.

Semiconductor packages and method of manufacturing the same

An embodiment semiconductor package includes a bare semiconductor chip, a packaged semiconductor chip adjacent the bare semiconductor chip, and a redistribution structure bonded to the bare semiconductor chip and the packaged semiconductor chip. The redistribution structure includes a first redistribution layer having a first thickness; a second redistribution layer having a second thickness; and a third redistribution layer between the first redistribution layer and the second redistribution layer. The third redistribution layer has a third thickness greater than the first thickness and the second thickness. The package further includes an underfill disposed between the bare semiconductor chip and the redistribution structure and a molding compound encapsulating the bare semiconductor chip, the packaged semiconductor chip, and the underfill.

Semiconductor packages and methods of forming same

Methods of forming connectors and packaged semiconductor devices are disclosed. In some embodiments, a connector is formed by forming a first photoresist layer over an interconnect structure, and patterning the first photoresist layer. The patterned first photoresist layer is used to form a first opening in an interconnect structure. The patterned first photoresist is removed, and a second photoresist layer is formed over the interconnect structure and in the first opening. The second photoresist layer is patterned to form a second opening over the interconnect structure in the first opening. The second opening is narrower than the first opening. At least one metal layer is plated through the patterned second photoresist layer to form the connector.

Connector formation methods and packaged semiconductor devices

Redistribution structures in semiconductor packages and methods of forming same

Embodiments of mechanisms for forming a package structure are provided. The package structure includes a semiconductor die and a substrate. The package structure includes a pillar bump and an elongated solder bump bonded to the semiconductor die and the substrate. A height of the elongated solder bump is substantially equal to a height of the pillar bump. The elongated solder bump has a first width, at a first horizontal plane passing through an upper end of a sidewall surface of the elongated solder bump, and a second width, at a second horizontal plane passing through a midpoint of the sidewall surface. A ratio of the second width to the first width is in a range from about 0.5 to about 1.1.

Mechanisms for forming hybrid bonding structures with elongated bumps

A semiconductor device includes a passivation layer formed on a semiconductor substrate, a protective layer overlying the passivation layer and having an opening, an interconnect structure formed in the opening of the protective layer, a bump formed on the interconnect structure, and a molding compound layer overlying the interconnect structure and being in physical contact with a lower portion of the bump.

Post-passivation interconnect structure and method of forming the same

The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a bump structure disposed on a first substrate and a molding compound in physical contact with the bump structure. The bump structure protrudes from the molding compound. A conductive region is on a second substrate and contacts the bump structure. A no-flow underfill (NUF) material is vertically between the molding compound and the second substrate and laterally surrounds the bump structure. The NUF material is separated from the molding compound.

Package assembly

In some embodiments, the present disclosure relates to a package assembly having a bump on a first substrate. A molding compound is on the first substrate and contacts sidewalls of the bump. A no-flow underfill layer is on a conductive region of a second substrate. The no-flow underfill layer and the conductive region contact the bump. A mask layer is arranged on the second substrate and laterally surrounds the no-flow underfill layer. The no-flow underfill layer contacts the substrate between the conductive region and the mask layer.

A method of fabricating an integrated fan-out package is provided. The method includes the followings. An integrated circuit component is mounted on a carrier. An insulating encapsulation is formed on the carrier to encapsulate sidewalls of the integrated circuit component. A plurality of conductive pillars are formed on the integrated circuit component and a dielectric layer is formed to cover the integrated circuit component and the insulating encapsulation, wherein the plurality of conductive pillars penetrate through the dielectric layer and are electrically connected to the integrated circuit component. A redistribution circuit structure is formed on the dielectric layer and the plurality of conductive pillars, wherein the redistribution circuit structure is electrically connected to the integrated circuit component through the plurality of conductive pillars, and the redistribution circuit structure and the insulating encapsulation are spaced apart by the dielectric layer.

Integrated fan-out package and method of fabricating the same

An embodiment device package includes first die and one or more redistribution layers (RDLs) electrically connected to the first die. The one or more RDLs extend laterally past edges of the first die. The device package further includes one or more second dies bonded to a first surface of the one or more RDLs and a connector element on the first surface of the one or more RDLs. The connector element has a vertical dimension greater than the one or more second dies. A package substrate is bonded to the one or more RDLs using the connector element, wherein the one or more second dies is disposed between the first die and the package substrate.

Substrate design for semiconductor packages and method of forming same

Semiconductor devices packages and methods are disclosed. In one embodiment, a package for a semiconductor device includes a substrate and a contact pad disposed on a first surface of the substrate. The contact pad has a first side and a second side opposite the first side. A conductive trace is coupled to the first side of the contact pad, and an extension of the conductive trace is coupled to the second side of the contact pad. A plurality of bond pads is disposed on a second surface of the substrate.

Semiconductor device packages and methods

Growing community of inventors

Tainan, Taiwan

Hung-Jen Lin