Taiwan Semiconductor Manufacturing Comp. Ltd.

Hung Der Su

Jhon Jhy Liaw

Jian-Hsing Lee

Jyh-Huei Chen

Shien-Yang Wu

Chrong Jung Lin

Yuan-Hung Chiu

Yi-Hsun Wu

Jong Chen

Ju-Wang Hsu

Yung-Shun Chen

Yi-Chun Huang

Mau-Lin Wu

Tung-Heng Shie

Wen Ting Chu

A method for forming a field effect transistor device employs a conformal spacer layer formed upon a gate electrode. The gate electrode is employed as a mask for forming a lightly doped extension region within the semiconductor substrate and the gate electrode and conformal spacer layer are employed as a mask for forming a source/drain region within the semiconductor substrate. An anisotropically etched shaped spacer material layer is formed upon the conformal spacer layer and isotropically etched to enhance exposure of the source/drain region prior to forming a silicide layer thereupon.

Spacer layer etch method providing enhanced microelectronic device performance

An I/O ESD protection circuit is provided utilizing a driver circuit, an ESD protection circuit, a Vcc/Vss protection circuit, and a clamping circuit. The driver circuit and the ESD protection circuit each comprise a NMOS cascode circuit. NMOS transistors and biasing resistive means comprise the Vcc/Vss protection circuit. The clamping circuit is a diode coupled between the I/O pad of the protection circuit and the gate of that NMOS transistor. In an ESD event the diode turns on the NMOS transistor of the Vcc/Vss protection circuit , thus clamping off the first transistor of both NMOS cascode circuits. The clamping inhibits the gate of those first two transistors to be coupled up by an ESD voltage and creates a parasitic bipolar transistor in each cascode circuit. The parasitic bipolar transistors provide a uniform current flow in the buried area of the P-well of both NMOS cascode circuits.

Gate ground circuit approach for I/O ESD protection

A method for making improved MOSFET structures is achieved. A Si.sub.3 N.sub.4 and a SiO.sub.2 layer are deposited and patterned to have openings for gate electrodes over device areas on a substrate. A second Si.sub.3 N.sub.4 layer is deposited and etched back to form arc-shaped sidewall spacers in the openings. An anti-punchthrough implant and a gate oxide are formed in the openings between the Si.sub.3 N.sub.4 sidewall spacers. A polysilicon layer is deposited and polished back to form gate electrodes. The SiO.sub.2 and the Si.sub.3 N.sub.4 layers, including the sidewall spacers, are removed to form free-standing gate electrodes that increase in width with height, and having arc-shaped sidewalls. An implant through the edges of the arc-shaped gate electrodes results in lightly doped source/drains that are graded both in junction depth and dopant concentration to reduce hot electron effects. A second SiO.sub.2 layer is deposited and etched back to form insulating sidewall spacers that include air spacers to reduce the gate-to-drain capacitance. Another implant is used to form source/drain contact areas. A salicide process is used which forms a silicide on the polysilicon gate electrodes and on the source/drain contact areas. The arc-shaped structure allows MOSFETs to be formed with reduced channel lengths while maintaining a wider silicide area on the gate electrodes for reduced resistance.

Method for making deep sub-micron mosfet structures having improved

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Sheh-Chung Village, Taiwan

Hung Der Su