Taiwan Semiconductor Manufacturing Comp. Ltd.

Hung-Che Liao

Kun-Tsang Chuang

Chih-Ming Lee

Hsin-Chi Chen

Chiang-Ming Chuang

Chien-Hsuan Liu

Chia-Ming Pan

Hung-Yu Chiu

Wei-Chung Lu

Yu-Chu Lin

Shih-Lu Hsu

Kun-tsang Chuang

Chih-Ming Chen

Po-Jen Wang

Ping-Hao Lin

Jyun-Guan Jhou

Kuo-Hsien Cheng

Tao-Sheng Chang

Hung-Ta Huang

Chi-Di An

Hsien-Wei Chin

Szu-Hsien Lu

Chun-Ching Wu

Yeong-Rong Chang

Jer-Yuan Sheu

Hsiang-Hui Tsai

Chih-Ming Huang

Feng-Ru Chang

Wen Jan Lin

Po-Yuan Su

Chao-Hsuan Pan

Wen-Tsung Chen

Chin-Kang Lee

Yeong-Kong Chang

A semiconductor device includes a stacked gate structure, a plurality of stacks and a first conductive layer. The stacks are disposed aside the stacked gate structure and arranged along both a first direction and a second direction perpendicular to the first direction, wherein the stacks are extended continuously along the first direction and segmented in the second direction. The first conductive layer is disposed between segmented portions of the stacks along the second direction, wherein top surfaces of the segmented portions of the stacks are higher than a top surface of the first conductive layer.

Semiconductor device having non-continuous wall structure surrounding a stacked gate structure including a conductive layer disposed between segmented portions of the wall structure

A semiconductor device is provided. The semiconductor device includes a substrate, a stacked gate structure, and a wall structure. The stacked gate structure is on the substrate and extending along a first direction. The wall structure is on the substrate and laterally aside the stacked gate structure. The wall structure extends along the first direction and a second direction perpendicular to the first direction. The stacked gate structure is overlapped with the wall structure in the first direction and the second direction.

Semiconductor device having a wall structure surrounding a stacked gate structure

A method of making a semiconductor structure includes depositing a first passivation material between adjacent conductive elements on a substrate, wherein a bottommost surface of the first passivation material is coplanar with a bottommost surface of each of the adjacent conductive elements. The method further includes depositing a second passivation material on the substrate, wherein the second passivation material contacts a sidewall of each of the adjacent conductive elements and a sidewall of the first passivation material, a bottommost surface of the second passivation material is coplanar with the bottommost surface of each of the adjacent conductive elements, and the second passivation material is different from the first passivation material.

Method of making a semiconductor structure

A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, at least one memory cell, and at least one word line. The raised dummy feature is present on the semiconductor substrate and defines a cell region on the semiconductor substrate. The memory cell is present on the cell region. The word line is present adjacent to the memory cell.

Semiconductor structure and method for forming the same

A semiconductor structure includes a substrate, first and second conductors, a passivation material, and a passivation sidewall block. The first and second conductors are on the substrate. The passivation material is between the first and second conductors. The passivation sidewall block is on sidewalls of the first and second conductors and the passivation material.

Semiconductor structure

A method of manufacturing a non-volatile memory is described. A substrate including a first region and a second region located at periphery of the first region is provided. A plurality of stacked structures are formed on the first region of the substrate. A wall structure is formed on the second region of the substrate. A conductive layer is formed over the substrate. A bottom anti-reflective coating is formed over the conductive layer. The bottom anti-reflective coating and the conductive layer are etched back. The conductive layer is patterned.

Non-volatile memory having an erase gate formed between two floating gates with two word lines formed on other sides and a method for forming the same

A method of fabricating semiconductor device includes forming a plurality of gate structures on a semiconductor substrate. A first inter layer dielectric layer is deposited on the gate structures. A first contact plug is formed in the first inter layer dielectric layer in between every two immediately adjacent gate structures. An etch stop layer is deposited on the first inter layer dielectric layer. A second inter layer dielectric layer is deposited on the first inter layer dielectric layer. A second contact plug is formed in the second inter layer dielectric layer aligning with the first contact plug. A metal layer is deposited overlying the second inter layer dielectric layer and the second contact plug.

Contact structure for high aspect ratio and method of fabricating the same

A flash memory cell structure includes a semiconductor substrate, a pad dielectric layer, a floating gate, a control gate, and a blocking layer. The pad dielectric layer is disposed on the semiconductor substrate. The floating gate is disposed over the pad dielectric layer, in which the floating gate has a top surface opposite to the pad dielectric layer, and the top surface includes at least one recess formed thereon. The control gate is disposed over the top surface of the floating gate. The blocking layer is disposed between the floating gate and the control gate.

Flash memory device having high coupling ratio

A semiconductor structure and a method for forming the semiconductor structure are provided. The method includes receiving a substrate with two sections of conductors thereon that are adjacent to each other, and a valley between the two sections of the conductors, filling the valley with a first passivation material to form a passivation valley, applying a second passivation material overlying the two sections of conductors and the passivation valley and over the substrate, and removing the second passivation material overlying the two sections of conductors and the passivation valley, and the second passivation material over the substrate but not in contact with the two sections of conductors and the passivation valley.

Method for fabricating semiconductor structure with passivation sidewall block

A non-volatile memory cell formed using damascene techniques includes a floating gate electrode that includes a recess lined with a control gate dielectric and filled with the control gate electrode material. The control gate material is a composite ONO, oxide-nitride-oxide sandwich dielectric in one embodiment. The floating gate transistors of the non-volatile memory cell include a high gate coupling ratio due to the increased area between the floating gate electrode and the control gate electrode.

Damascene non-volatile memory cells and methods for forming the same

A novel semiconductor device structure includes a first-conductivity-type semiconductor substrate, an isolated region, a first-conductivity-type MOS region, and a second-conductivity-type MOS region. A first-conductivity-type MOS transistor locates in the first-conductivity-type MOS region with a second-conductivity-type well surrounding, and a first-conductivity-type deep well surrounding the second-conductivity-type well with a second-conductivity-type deep well surrounding. In the second-conductivity-type MOS region, a second-conductivity-type MOS transistor is formed with a first-conductivity-type well surrounding. The first-conductivity-type deep well and the second-conductivity-type deep well are sufficiently reducing the noise and current leakage from other devices or from the semiconductor substrate.

Semiconductor device structure and method for manufacturing the same

An integrated circuit and a method of fabricating the integrated circuit are provided. In various embodiments, the integrated circuit includes a semiconductor substrate, at least one deep n-well in the semiconductor substrate, at least one p-channel metal-oxide-semiconductor transistor in the deep n-well, at least one n-channel metal-oxide-semiconductor transistor outside of the deep n-well, an first interconnect structure, and a protection component. Both of the p-channel metal-oxide-semiconductor transistor and the n-channel metal-oxide-semiconductor transistor are disposed in the semiconductor substrate, and are electrically coupled by the first interconnect structure. The protection component is disposed in the semiconductor substrate, wherein the protection component is electrically coupled to the deep n-well.

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Tainan, Taiwan

Hung-Che Liao