Taiwan Semiconductor Manufacturing Comp. Ltd.

Hung-Chang Hsieh

Ming-Feng Shieh

Wang-Pen Mo

Chun-Wei Chang

Chun-Chang Chen

Chih-Chien Wang

Jhun Hua Chen

Shih-Ming Chang

Yu-Hsien Lin

Wen-Hung Tseng

Anthony Yen

Chi-Lun Lu

Yung-Sheng Huang

Chang-Cheng Hung

Tzung-Hua Lin

Hsin-Chang Lee

Chia-Jen Chen

Hua-Tai Lin

Ya Hui Chang

Ming-Jhih Kuo

Chia-Shiung Tsai

Ru-Gun Liu

Shang-Chieh Chien

Jeng-Horng Chen

Shinn-Sheng Yu

Tsai-Sheng Gau

Chia-Hao Yu

Chen-Cheng Kuo

Chia-Chen Chen

Wen-Chuan Wang

Shih-Chi Fu

Feng-Jia Shiu

Chun-Yi Lee

Sheng-Chi Chin

Yao-Ching Ku

Kuei-Liang Lu

Han-Wei Wu

Shun-Shing Yang

Jui-Ching Wu

Hung-Chung Chien

Ren-Guey Hsieh

Hong-Da Lin

Shu-Fang Chen

Chuan-Ling Wu

Ken Wu

Luke Hsu

Han-Chang Hsieh

Weng-Hung Tseng

Jen-Cheng Liu

Shau-Lin Shue

Syun-Ming Jang Jang

Chih-Ming Lai

Jin-Yuan Lee

Jhon-Jhy Liaw

Li-Jui Chen

Chung-Ju Lee

Tien-I Bao

Kong-Beng Thei

Hun-Jan Tao

Huan-Just Lin

Ta-Cheng Lien

Yun-Yue Lin

Tsu Shih

Chih-Ming Ke

Chu-Yun Fu

Hsien-Cheng Wang

Yi-Fan Chen

Fang-Cheng Chen

Chien-Wen Lai

Fu-Jye Liang

Chen-Yu Chen

Hsiang-Lin Chen

Ming-Che Wu

Jhih-Yu Wang

Chin-Min Huang

Chia-Cheng Chang

Chia-Chieh Lin

Cherng-Shyan Tsay

Wei-De Ho

Ying-Ying Wang

Ching-Huang Chen

Chih-Cheng Chin

Yih-Chen Su

Yuan-Yen Lo

Tyng-Hao Hsu

Yu-Lung Tung

Chi-Yuan Sun

Ai-Jen Hung

Lin-Hung Shiu

Chu-Wei Chang

Chi-Tien Chen

Grace H Ho

Spencer Lin

Irene Ho

Cheng-Hsien Chuang

Vinvent Yu

Hsen-Lin Wu

Li-Heng Chou

Jung Ting Chen

Chih-Chen Chin

A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A first conductive feature and a second conductive feature are provided. A first hard mask (HM) is formed on the first conductive feature. A patterned dielectric layer is formed over the first and the second conductive features, with first openings to expose the second conductive features. A first metal plug is formed in the first opening to contact the second conductive features. A second HM is formed on the first metal plugs and another patterned dielectric layer is formed over the substrate, with second openings to expose a subset of the first metal plugs and the first conductive features. A second metal plug is formed in the second openings.

Method of semiconductor integrated circuit fabrication

The present disclosure provides a lithography system. The lithography system includes an exposing module configured to perform a lithography exposing process using a mask secured on a mask stage; and a cleaning module integrated in the exposing module and designed to clean at least one of the mask and the mask stage using an attraction mechanism.

Lithography system with an embedded cleaning module

A method of fabricating a fin-like field-effect transistor device is disclosed. The method includes forming mandrel features over a substrate and performing a first cut to remove mandrel features to form a first space. The method also includes performing a second cut to remove a portion of mandrel features to form a line-end and an end-to-end space. After the first and the second cuts, the substrate is etched using the mandrel features, with the first space and the end-to-end space as an etch mask, to form fins. Depositing a space layer to fully fill in a space between adjacent fins and cover sidewalls of the fins adjacent to the first space and the end-to-end space. The spacer layer is etched to form sidewall spacers on the fins adjacent to the first space and the end-to-end space and an isolation trench is formed in the first space and the end-to-end space.

Method of making a FinFET device

Methods are disclosed herein for fabricating semiconductor devices having shared source/drain contacts. An exemplary semiconductor device includes a high-k/metal gate stack disposed over a substrate. The high-k/metal gate stack is disposed between a first source/drain feature and a second source/drain feature. A first spacer set is disposed along sidewalls of the high-k/metal gate stack. A first interlevel dielectric (ILD) layer is disposed over the substrate. Upper portions of the first spacer set that extend above the first ILD layer have a tapered width. A second spacer set is disposed on the upper portions of the first spacer set and over the first ILD layer. A second ILD layer is disposed over the first ILD layer. A contact feature extends through the second ILD layer to the first source/drain feature and the second source/drain feature. The contact feature spans uninterrupted between the first source/drain feature and the second source/drain feature.

Method of forming source/drain contact

Methods for fabricating semiconductor devices are disclosed. An exemplary method includes forming first spacers along sidewalls of a gate structure that is disposed over a substrate and between source/drain features. A first dielectric layer is formed over the substrate and recessed to expose upper portions of the first spacers. A spacer layer is then formed over the upper portions of the first spacers. A second dielectric layer is formed over the spacer layer, and a patterned masking layer is formed over the second dielectric layer. The second dielectric layer, the spacer layer, and the first dielectric layer are patterned. For example, exposed portions of the second dielectric layer, the spacer layer (forming second spacers disposed along the upper portions of the first spacers), and the first dielectric layer are etched to form a trench exposing the gate structure and the source/drain features. The trench is filled with a conductive material.

A lithography method is provided in accordance with some embodiments. The lithography method includes forming a surface modification layer on a substrate, the surface modification layer including a hydrophilic top surface; coating a photoresist layer on the surface modification layer; and developing the photoresist layer, thereby forming a patterned photoresist layer.

Lithography method with surface modification layer

A method provides an integrated circuit (IC) substrate having first and second alignment marks defined in a first pattern layer, and third and fourth alignment marks defined in a second pattern layer. The first and second alignment marks are illuminated, through a photomask, with a first light to determine a first layer alignment error including a first alignment error and a second alignment error. The first alignment error has more weight than the second alignment error in determining the first layer alignment error. The third and fourth alignment marks are illuminated with a second light to determine a second layer alignment error including a third alignment error in relation to the third alignment mark and a fourth alignment error in relation to the fourth alignment mark. The third alignment error has more weight than the fourth alignment error in determining the second layer alignment error.

System and method for lithography alignment

A method of fabricating a fin-like field-effect transistor (FinFET) device is disclosed. The method includes forming a mandrel features over a substrate, the mandrel feature and performing a coarse cut to remove one or more mandrel features to form a coarse space. After the coarse cut, the substrate is etched by using the mandrel features, with the coarse space as an etch mask, to form fins. A spacer layer is deposited to fully fill in a space between adjacent fins and cover sidewalls of the fins adjacent to the coarse space. The spacer layer is etched to form sidewall spacers on the fins adjacent to the coarse space. A fine cut is performed to remove a portion of one or more mandrel features to form an end-to-end space. An isolation trench is formed in the end-to-end space and the coarse space.

A method includes depositing an ESL on a substrate; patterning the ESL such that a first region of the substrate is covered thereby and a second region of the substrate is exposed within an opening of the etch stop layer; depositing a first dielectric layer on the ESL in the first region and on the substrate in the second region; patterning the first dielectric layer to form a first trench through the first dielectric layer in the first region; forming a metal feature in the first trench; depositing a second dielectric layer over the metal feature in the first region and over the first dielectric layer in the second region; and performing a patterning process to form a second trench through the second dielectric layer in the first region, and to form a third trench through the second and first dielectric layers in the second region.

Integrated circuit structure and method forming trenches with different depths

A method for forming a photoresist layer on a semiconductor device is disclosed. An exemplary includes providing a wafer. The method further includes spinning the wafer during a first cycle at a first speed, while a pre-wet material is dispensed over the wafer and spinning the wafer during the first cycle at a second speed, while the pre-wet material continues to be dispensed over the wafer. The method further includes spinning the wafer during a second cycle at the first speed, while the pre-wet material continues to be dispensed over the wafer and spinning the wafer during the second cycle at the second speed, while the pre-wet material continues to be dispensed over the wafer. The method further includes spinning the wafer at a third speed, while a photoresist material is dispensed over the wafer including the pre-wet material.

Method of forming a photoresist layer

A device for semiconductor fabrication includes a substrate and a layer formed over the substrate, wherein the layer includes an alignment mark. The alignment mark includes a first plurality of elongated members that are oriented lengthwise along a first direction and are distributed along a second direction. The alignment mark further includes a second plurality of elongated members that are oriented lengthwise along a third direction perpendicular to the first direction and are distributed along the second direction, wherein the second direction is different from each of the first and third directions.

Lithography alignment marks

The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout including a first main feature and inserting a first plurality of scattering bars in the IC design layout to form a first circular pattern of scattering bars around the first main feature. The first main feature is positioned at a center portion of the first circular pattern of scattering bars.

Method of lithography process with inserting scattering bars

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Hsin-Chu, Taiwan

Hung-Chang Hsieh