Samsung Electronics Co., Ltd.

Hun-Hyeoung Lim

Sang-Hoon Lee

Hyeon-Deok Lee

Young-sub You

Bong-hyun Kim

Woo-Sung Lee

Yong-Woo Hyung

A tunnel dielectric layer is formed on a semiconductor device. A floating gate layer is formed on the tunnel dielectric layer. An intergate dielectric layer (ONO layer) is formed on the floating gate layer. An in-situ doped silicon is deposited on the intergate dielectric layer to form a control gate layer and then, an annealing is carried out. The control gate layer, the intergate dielectric layer, and the floating gate layer are patterned through a photolithographic process. The phase transformation of the control gate silicon layer does not occur during a subsequent gate oxidation process to reduce the thickness variation of the ONO layer, thereby improving endurance and bake retention characteristics of the semiconductor device.

Method of forming a gate of a non-volatile memory device

A semiconductor device including a stacked gate having stacked gate sidewalls and an oxide/nitride/oxide (ONO) interlayer dielectric is manufactured by pre-annealing the stacked gate in a first atmosphere that includes nitrogen. At least a portion of the stacked gate sidewalls of the stacked gate that has been pre-annealed is oxidized. Post-annealing is then performed on the stacked gate including the stacked gate sidewalls that have been oxidized, in a second atmosphere that includes nitrogen.

Methods for manufacturing stacked gates including oxide/nitride/oxide (ONO) interlayer dielectrics using pre-annealing and/or post-annealing in nitrogen

Growing community of inventors

Gyeonggi-do, South Korea

Hun-Hyeoung Lim