Taiwan Semiconductor Manufacturing Comp. Ltd.

Industrial Technology Research Institute

United Microelectronics Corp.

Hun-Hsien Chang

Ming-Dou Ker

Tung-Yang Chen

Wen-Tai Wang

Chung-Hui Chen

Chung-Yuan Lee

Joe Ko

Chung-Yu Wu

Wen-Yu Lo

Chen-Chia Wang

The present invention comprises an ESD clamp circuit used in an integrated circuit with plural power supply. The ESD clamp circuit, connected between core voltage source and low voltage source, is fabricated by a process which fabricates core circuit. The ESD clamp circuit has a low trigger voltage, so it can conduct large current to protect the core circuit before the core circuit is damaged.

VDDCORE to VSS ESD clamp made of core device

An object of the present invention is to provide a charged-device model (CDM) electrostatic discharge (ESD) protection circuit for an integrated circuit (IC). The ESD protection circuit comprises an ESD clamp device and a functional component. The ESD clamp device is coupled to a pad and a substrate having a first conductivity type. Under normal power operation, the ESD clamp device is closed. The functional component is formed on the substrate and coupled to the pad. The functional component has a first well having the first conductivity type and an isolating region having a second conductivity type for isolating the first well from the substrate. Under normal power operation, the functional component transmits signals between the IC and an external linkage. During an CDM ESD event, the CDM charges accumulated in the substrate are discharged via the ESD clamp circuit. Hence, the functional component is protected.

CDM ESD protection design using deep N-well structure

High-voltage-tolerant ESD protection devices (ESDPD) for deep-submicron CMOS process were activated between LDD implanting and forming sidewall spacers. ESD-Implant (ESDI) regions are located at the ESDPD, without covering the center region under the drain contact (DC). The ESDI LDD concentration and doping profile are deep to contain drain diffusion. Regions with the ESDI have a high junction breakdown voltage (JBV) and a low junction capacitance. After forming gate sidewall spacers, high doping concentration ions implanted into active D/S regions formed a shallower doping profile of the D/S diffusion. The drain has a JBV as without this ESDI, so the ESD current (ESDC) is discharged through the center junction region under the DC to bulk, far from the ESDPD surface channel region. The ESDPD sustains a high ESD level. In an original drain JBV of an MOS this ESDI method is unchanged, i.e. the same as that having no such ESDI, so it can be used in I/O circuits with high-voltage signals in the deep-submicron CMOS. The ESD level of the IO ESDPD improves. The ESD discharge current path in the MOS device structure improves the ESD level in the output buffer MOS. ESDI regions are located at the output MOS devices, without covering the region under the DC. Regions under the DC without this ESDI have an unchanged JBV, so the ESDC discharges through the junction region under the DC to bulk. The original drain JBV of the output MOS with this ESDI method is unchanged, which is still the same as that having no such ESDI, to be used in the I/O circuits with high-voltage (5V) input signals in the deep-submicron CMOS with 3.3V or 2.5V VDD. This applies to diodes, FOD and lateral BJT devices.

ESD implantation in deep-submicron CMOS technology for high-voltage-tolerant applications

An ESD protection component with a deep-N-well structure in CMOS technology and the relevant circuit designs are proposed in this invention. The ESD protection component comprises a lateral silicon controlled rectifier (SCR) and a deep N-well. The SCR comprises a P-type layer, an N-type layer, a first N-well and a first P-well. The P-type layer is used as an anode of the SCR; the N-type layer is used as a cathode of the SCR; the first N-well is located between the P-type layer and the N-type layer and is contacted with the P-type layer; and the first P-well is contacted to the first N-well and the N-type layer. The deep N-well is located between the first P-well and the P-substrate, and is used to isolate the electric connection between the P-substrate and the first P-well. A plurality of these ESD protection components arbitrarily connected in series increases the total holding voltage of ESD protection circuit, thus preventing occurrences of latch-up.

SCR devices with deep-N-well structure for on-chip ESD protection circuits

A diode string with very low leakage current is used in power supply ESD clamp circuits. By adding an CMOS-Controlled Lateral SCR device into the cascaded diode string, the leakage current of this new diode string with 6 cascaded diodes under 5 Volts (3.3 Volts) forward bias can be controlled below 2.1 (1.07) nA at a temperature of 125&deg; C. in a 0.35 &mgr;m silicide CMOS process. The holding voltage of this design with the CMOS-Controlled Lateral SCR can be linearly adjusted by changing the number of the cascaded diodes in the diode string for the application among the power lines with different voltage levels. The ESD level of this ESD clamp circuit is greater than 8,000 Volts in the Human-Body-Model ESD test. The diodes string is suitable for portable or low-power CMOS Integrated Circuit (IC) devices.

Low-leakage diode string for use in the power-rail ESD clamp circuits

Novel PMOS-bound and NMOS-bound diodes for ESD protection, together with their application circuits, are disclosed in this invention. The PMOS-bound (or NMOS bound) diode has a PMOS (or an NMOS) structure. The source/drain region enclosed by the control gate of the PMOS (or NMOS) is used as an anode (or cathode) of the PMOS-bound (or NMOS-bound) diode. The base of the PMOS (or NMOS) is used as a cathode (or anode) of the PMOS-bound (or NMOS-bound) diode. The control gate prevents any shallow trench isolation region from forming beside the p-n junction of the PMOS-bound (or NMOS-bound) diode, such that the ESD sustaining level doesn't suffer from the formation of the STI regions. Furthermore, by ensuring proper bias to the control gate during an ESD event, the turn-on speed of the PMOS-bound or NMOS-bound diode can be increased, such that the overall ESD level of an IC chip is improved. By applying the PMOS-bound or NMOS-bound diode, ESD protection circuits for I/O buffer, power-rail ESD clamping circuits and whole-chip ESD protection systems are also provided.

ESD protection networks with NMOS-bound or PMOS-bound diode structures in a shallow-trench-isolation (STI) CMOS process

In this invention, a novel substrate-triggered technique is proposed to effectively improve the electrostatic discharge (ESD) robustness of integrated circuit (IC) products. The ESD protection circuit derived from the substrate-triggered technique is comprised of a metal-oxide-semiconductor (MOS) transistor and an ESD detection circuit. The MOS transistor is composed of a bulk region, a gate, a source region coupled to a power rail, and a drain region couple to a pad. The source region, the bulk region and the drain region further construct a parasitic bipolar junction transistor (BJT) The ESD detection circuit is located between, and connected to, the power rail and the pad. During normal operation, the ESD detection circuit maintains the coupling of the bulk region to the first power rail. During an ESD event, the ESD detection circuit biases the bulk region to trigger the BJT thereby releasing ESD stress. Research and experiment demonstrate the substrate-triggered technique can substantially improve the ESD protection level of an MOS transistor.

Substrate-triggered technique for on-chip ESD protection circuit

An implanting method forms high-voltage-tolerant ESD protection devices (ESDPD) for deep-submicron CMOS process activated between LDD implanting and forming sidewall spacers. ESD-Implant (ESDI) regions are located at the ESDPD, without covering the center region under the drain contact (DC). The ESDI LDD concentration and doping profile are deep to contain drain diffusion. Regions with the ESDI have a high junction breakdown voltage (JBV) and a low junction capacitance. After forming gate sidewall spacers, implant high doping concentration ions into active D/S regions forming a shallower doping profile of the D/S diffusion. The drain has a JBV as without this ESDI, so the ESD current (ESDC) is discharged through the center junction region under the DC to bulk, far from the ESDPD surface channel region. The ESDPD sustains a high ESD level. The original drain JBV of an MOS with this ESDI method is unchanged, i.e. the same as that having no such ESDI, so it can be used in I/O circuits with high-voltage signals in the deep-submicron CMOS. The ESD level of the I/O ESDPD improves. This method applies to high-voltage-tolerant I/O pins in a deep-submicron CMOS. The ESD discharge current path in the MOS device structure improves the ESD level in the output buffer MOS. ESDI regions are located at the output MOS devices, without covering the region under the DC. The method has a LDD concentration, so regions with this ESDI have a higher JBV and a lower junction capacitance. Regions under the DC without this ESDI have an unchanged JBV, so the ESDC discharges through the junction region under the DC to bulk.

ESD implantation method in deep-submicron CMOS technology for high-voltage-tolerant applications with light-doping concentrations

A process for forming an implanted ESD region, and for forming metal silicide blocking regions, using the same photolithographic mask for definition of these regions, has been developed. The process features the formation of an implanted ESD region, defined by a photoresist shape which in turn had been formed via exposure of a negative photoresist layer, using a specific photolithographic mask. Metal silicide regions are subsequently formed on regions of a semiconductor substrate, exposed in openings in an insulator layer, with the openings in the insulator layer defined via a photoresist shape, which in turn had been formed via exposure of a positive photoresist layer, using the same photolithographic mask previously used for definition of the implanted ESD region. In this invention we use only one photolithographic mask in the CMOS process to fabricate an ESD device having ESD implanted and metal silicide blocking regions, which can sustain higher ESD stress.

Method of fabricating ESD protection device by using the same photolithographic mask for both the ESD implantation and the silicide blocking regions

An apparatus of preventing integrated circuits from interfering by electrostatic-discharge (ESD), applied in an internal circuit and an input pad, both coupled with a first power line and a second power line, comprises a voltage clamp circuit and a voltage bias circuit. The voltage clamp circuit, with a transistor, connects to the second power line for clamping potential level through the voltage clamp circuit. The voltage bias circuit, with at least one diode coupled in series, connects to the voltage clamp circuit and the first power line for biasing the voltage clamp circuit to the second power line.

Gate-coupled ESD protection circuit without transient leakage

An ESD protection circuit is connected to an integrated circuit to dissipate an electrostatic charge from an ESD source placed in contact with two terminals of the integrated circuit to prevent damage to the integrated circuits. The ESD protection circuit has a ESD shunting circuit for shunting the electrostatic charge from integrated circuit. The ESD shunting circuit has a first port connected to one terminal of the integrated circuit, a second port connected to another terminal of the integrated circuit, and a third port. The ESD protection circuit additionally has an ESD detection circuit. The ESD detection circuit has a first input port connected to the one terminal of the integrated circuit, a second input port connected to the other terminal of the integrated circuit, and an output port connected to the third port of the ESD shunting circuit. When the ESD detection circuit detects the presence of the electrostatic charge from the ESD source, the ESD detection circuit generates an excess voltage at the third port that will damage the ESD shunting circuit. Finally The ESD protection circuit has a voltage clamping circuit connected between the third port of the ESD shunting circuit and one of the terminals of the integrated circuit to prevent the generation of the excess voltage at the third port of the ESD shunting circuit.

ESD protection circuit without overstress gate-driven effect

In this invention, a new whole-chip ESD protection scheme with the ESD buses has been proposed to solve the ESD protection issue of the CMOS IC having a large number of separated power lines. Multiple ESD buses, which are formed by the wide metal lines, have been added into the CMOS IC having a large number of separated power lines. The bi-directional ESD-connection cells are connected between the separated power lines and the ESD buses, but not between the separated power lines. The ESD current on the CMOS IC with more separated power lines are all conducted into the ESD buses, therefore the ESD current can be conducted by the ESD buses away from the internal circuits and quickly discharged through the designed ESD protection devices to ground. By using this new whole-chip ESD protection scheme with the ESD buses, the CMOS IC having more separated power lines can be still safely protected against ESD damages.

ESD bus lines in CMOS IC's for whole-chip ESD protection

CMOS VLSI chips with pin counts greater than 100 often have multiple power pins to supply sufficient current for circuit operations. In mixed voltage ICs there are separated power pins with different power supplies for specified power operations, and in these ICs the power supplies for the digital and analog circuits are often separated due to noise considerations. In such ICs with separated power pins, the interface circuits between the circuits with different power pins are vulnerable to ESD (electrostatic discharge) stress. Even though there are suitable ESD protection circuits around the input and output pins of the IC, unexpected ESD damage still happens to the interface circuits between the circuits with different power pins, so that a whole-chip ESD protection arrangement using bi-directional SCRs is provided to protect the CMOS ICs against ESD damage. The bi-directional SCRs are placed between the separated power lines of the CMOS IC to provide ESD current discharging paths between the separated power lines. Thus, the vulnerable internal circuits and interface circuits between the different power pins are rendered remote from the ESD damage. The present ESD protection arrangement can be applied to chips having multiple or mixed-voltage power pins.

Whole-chip ESD protection for CMOS ICs using bi-directional SCRs

An MOS-controlled, lateral SCR device including a semiconductor substrate of a first doping type; a first well region formed in the substrate and being of a second doping type which is different from the first doping type; a second well region formed in the substrate, being of the second doping type, and being spaced apart from the first well region so as to define an intermediate region separating the first and second well regions from each other; a first region formed within the first well region and extending into the intermediate region between the first and second well regions, the first region being of the second doping type; a second region formed within the second well region and extending into the intermediate region between the first and second well regions, the second region being of the second doping type; and a control gate bridging over the intermediate region between the first and second regions.

CMOS output buffer with CMOS-controlled lateral SCR devices

In this invention, a whole-chip ESD protection scheme with the SCR string or the SCR/diode-mixed string are proposed to protect the mixed-voltage CMOS IC's against the ESD damage. The SCR string or the SCR/diode-mixed string is placed between the separated power lines. The ESD current is arranged to be discharged through the SCR string or the SCR/diode-mixed string and the ESD clamps between the power lines. Therefore, the internal circuits and the interface circuits between the circuits with different power supplies can be prevented from ESD damages. The number of the SCR's or the diodes in the SCR string or the SCR/diode-mixed string connected between the different power lines is dependent on the voltage difference between the different power supplies in the mixed-voltage CMOS IC's. When the IC is in the normal operating conditions, such SCR string or the SCR/diode-mixed string between the different power lines is kept off to maintain the independence of the power supplies in the mixed-voltage COMS IC.

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Taipei Hsien, Taiwan

Hun-Hsien Chang