Applied Materials, Inc.

Varian Semiconductor Equipment Associates, Inc.

Huixiong Dai

Christopher S Ngai

Ellie Y Yieh

Mangesh Bangar

Srinivas D Nemani

Christopher Dennis Bencher

John J Hautala

Wenhui Wang

Simon Ruffell

Bencherki Mebarki

Daniel Lee Diehl

Adam Brand

Yongmei Chen

Steven Hiloong Welch

Ludovic Godet

Dmitry Lubomirsky

Mehul B Naik

Xianmin Tang

Yong Cao

Weimin Zeng

Peng Xie

Joseph C Olson

Abhilash J Mayur

Bruce E Adams

Mahendra Pakala

Anthony Renau

He Ren

Chando Park

Chentsau Chris Ying

Hao Chen

Joung Joo Lee

Sahil Patel

Lin Xue

Tristan Yonghui Ma

Jaesoo Ahn

Jong Mun Kim

Tingjun Xu

Timothy B Michaelson

Minrui Yu

Li Yan Miao

Christopher Siu Wing Ngai

Jun Lang

Kelly E Hollar

Jaujiun Chen

Xumou Xu

Nitin K Ingle

David P Thompson

Khoi A Phan

Robert Jan Visser

Deenesh Padhi

Douglas A Buchberger, Jr

Pramit Manna

Bok Hoen Kim

Rongjun Wang

Kadthala Ramaya Narendrnath

Hui W Chen

Lin Zhang

Keith Tatseun Wong

Raymond Hoiman Hung

Liqi Wu

Patrick M Martin

Michael Duane

Tejinder Singh

Jen Shu

Subhash Deshmukh

Wenyu Zhang

Alan Tso

Jingjing Xu

Byeong Chan Lee

Ke Chang

Chorng-Ping Chang

Susie Xiuru Yang

Gautam Pisharody

Liyan Miao

Kenneth MacWilliams

Lancelot Huang

Jiahua Yu

A post lithography resist treatment apparatus for treating a substrate having a resist layer thereon with a fluid layer thereover includes at least one post exposure bake chamber having a substrate support having a substrate support surface thereon, and an electrode, the electrode comprising an electrode body having a substrate support facing side, the substrate support facing side having at least one recess extending inwardly thereof, and at least one projection adjacent to the recess having a substrate support facing surface thereon, wherein the substrate support is moveable to position a substrate, when supported thereon, such that an fluid layer disposed on the substrate contacts the substrate support facing surface of the projection but does not fill the recess with fluid, and the substrate facing surface of the electrode body is spaced from the substrate.

System architecture of manufacturing of semiconductor wafers

A method for processing a substrate is described. The method includes forming a metal containing resist layer onto a substrate, patterning the metal containing resist layer, and performing a post exposure bake on the metal containing resist layer. The post exposure bake on the metal containing resist layer is a field guided post exposure bake operation and includes the use of an electric field to guide the ions or charged species within the metal containing resist layer. The field guided post exposure bake operation may be paired with a post development field guided bake operation.

Metal oxide resist patterning with electrical field guided post-exposure bake

Methods of forming and processing semiconductor devices which utilize a three-color hardmask process are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications. More particularly, certain embodiments relate to the formation of self-aligned gate contacts through the selective deposition of a fill material.

Contact over active gate structure

Embodiments of the present disclosure generally include spin-orbit torque magnetoresistive random-access memory (SOT-MRAM) devices and methods of manufacture thereof. The SOT-MRAM devices described herein include an SOT layer laterally aligned with a magnetic tunnel junction (MTJ) stack and formed over a trench in an interconnect. Thus, the presence of the SOT layer outside the area of the MTJ stack is eliminated, and electric current passes from the interconnect to the SOT layer by SOT-interconnect overlap. The devices and methods described herein reduce the formation of shunting current and enable the MTJ to self-align with the SOT layer in a single etching process.

Spin-orbit torque MRAM structure and manufacture thereof

A method for enhancing a photoresist profile control includes applying a photoresist layer comprising a photoacid generator on an underlayer disposed on a material layer, exposing a first portion of the photoresist layer unprotected by a photomask to light radiation in a lithographic exposure process, providing a thermal energy to the photoresist layer in a post-exposure baking process, applying an electric field or a magnetic field while performing the post-exposure baking process, and drifting photoacid from the photoresist layer to a predetermined portion of the underlayer under the first portion of the photoresist layer.

Photoresist patterning process

A method for enhancing the depth of focus process window during a lithography process includes applying a photoresist layer comprising a photoacid generator on a material layer disposed on a substrate, exposing a first portion of the photoresist layer unprotected by a photomask to light radiation in a lithographic exposure process, providing a thermal energy to the photoresist layer in a post-exposure baking process, applying an electric field or a magnetic field while performing the post-exposure baking process, and dynamically changing a frequency of the electric field as generated while providing the thermal energy to the photoresist layer.

Lithography process window enhancement for photoresist patterning

A method of patterning a substrate. The method may include providing a surface feature on the substrate, the surface feature having a first dimension along a first direction within a substrate plane, and a second dimension along a second direction within the substrate plane, wherein the second direction is perpendicular to the first direction; and directing first ions in a first exposure to the surface feature along the first direction at a non-zero angle of incidence with respect to a perpendicular to the substrate plane, in a presence of a reactive ambient containing a reactive species; wherein the first exposure etches the surface feature along the first direction, wherein after the directing, the surface feature retains the second dimension along the second direction, and wherein the surface feature has a third dimension along the first direction different than the first dimension.

Techniques to engineer nanoscale patterned features using ions

Methods and apparatuses for minimizing line edge/width roughness in lines formed by photolithography are provided. In one example, a method of processing a substrate includes applying a photoresist layer comprising a photoacid generator to on a multi-layer disposed on a substrate, wherein the multi-layer comprises an underlayer formed from an organic material, inorganic material, or a mixture of organic and inorganic materials, exposing a first portion of the photoresist layer unprotected by a photomask to a radiation light in a lithographic exposure process, and applying an electric field or a magnetic field to alter movement of photoacid generated from the photoacid generator substantially in a vertical direction.

Film structure for electric field guided photoresist patterning process

Embodiments of the present disclosure generally relate to apparatus and methods for verification and re-use of process fluids. The apparatus generally includes a tool for performing lithography, and a recirculation path coupled to the tool. The recirculation path generally includes a collection unit coupled at first end to a first end of the tool, and a probe coupled at a first end to a second end of the collection unit, the probe for determining one or more characteristics of a fluid flowing from the tool. The recirculation path of the apparatus further generally includes a purification unit coupled at a first end to a third end of the collection unit, the purification unit further coupled at a second end to a second end of the probe, the purification unit for changing a characteristic of the fluid.

Apparatus and methods for verification and re-use of process fluids

In some embodiments, a method of processing a substrate disposed atop a substrate support in a physical vapor deposition process chamber includes: (a) forming a plasma from a process gas within a processing region of the physical vapor deposition chamber, wherein the process gas comprises an inert gas and a hydrogen-containing gas to sputter silicon from a surface of a target within the processing region of the physical vapor deposition chamber; and (b) depositing an amorphous silicon layer atop a first layer on the substrate, wherein adjusting the flow rate of the hydrogen containing gas tunes the optical properties of the deposited amorphous silicon layer.

Methods for depositing amorphous silicon layers or silicon oxycarbide layers via physical vapor deposition

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Huixiong Dai