International Business Machines Corporation

Globalfoundries Inc.

Adeia Semiconductor Bonding Technologies Inc.

State University of New York

Stmicroelectronics Gmbh

Huiming Bu

Tenko Yamashita

Junli Wang

Dechao Guo

Brent A Anderson

Veeraraghavan S Basker

Kangguo Cheng

Sivananda K Kanakasabapathy

Fee Li Lie

Theodorus E Standaert

Terence B Hook

Andrew Mark Greene

Peng Xu

Balasubramanian Pranatharthiharan

Ruilong Xie

Xuefeng Liu

Effendi Leobandung

Vijay Narayanan

Bruce Bennett Doris

Chun-chen Yeh

Shogo Mochizuki

Keith Kwong Hon Wong

Andres Bryant

Michael Patrick Chudzik

Huimei Zhou

Satya N Chakravarti

Junjun Li

Nicolas J Loubet

William K Henson

Gen Tsutsui

Siyuranga O Koswatta

Liying Jiang

Reinaldo Ariel Vega

Chung-Hsun Lin

Wilfried Haensch

Naim Moumen

Devendra K Sadana

Ali Khakifirooz

Edward J Nowak

Stephen W Bedell

Chen Zhang

Robert J Gauthier, Jr

Shom Ponoth

Praneet Adusumilli

Zuoguang Liu

Hiroaki Niimi

Eduard Albert Cartier

Renee Tong Mo

Unoh Kwon

Siddarth A Krishnan

Vamsi Krishna Paruchuri

Balasubramanian S Haran

Chun Wing Yeung

Chun-Chen Yeh

Barry P Linder

Wesley Charles Natzle

Johnathan E Faltermeier

Miaomiao Wang

Stefan Schmitz

Young-Hee Kim

Michelle Leigh Steen

Mukesh Vijay Khare

Hui-feng Li

Wei He

Takashi Ando

Ramachandra Divakaruni

Ruqiang Bao

Jingyun Zhang

Robert Russell Robison

JunJun Li

Kisik Choi

John Ryan Sporre

Rajasekhar Venigalla

Albert Manhee Chu

Gauri V Karve

Stuart A Sieg

John Christopher Arnold

Prasanna Khare

Albert M Young

Hongwen Yan

Somnath Ghosh

Ricardo Alves Donaton

Huiling Shang

Kai Zhao

Sagarika Mukesh

Mona Abdulkhaleg Ebrish

Yoo-Mi Lee

An in-situ chip design is provided for self-heating free characterization of a device under test (DUT) with a short time constant. The in-situ chip design includes a pulse generator configured to output a pulse to the DUT and a buffering circuit arranged between the pulse generator and the DUT. The buffering circuit includes a first switch and an adjustable buffer circuit in parallel with the first switch and being controllable to apply one of various degrees of buffering to the pulse.

In-situ chip design for pulse IV self-heating evaluation

A device comprises a first interconnect structure, a second interconnect structure, a first cell comprising a first transistor, a second cell comprising a second transistor, a first contact connecting a source/drain element of the first transistor to the first interconnect structure, and second contact connecting a source/drain element of the second transistor to the second interconnect structure. The first cell is disposed adjacent to the second cell with the first transistor disposed adjacent to the second transistor. The first and second cells are disposed between the first and second interconnect structures.

Backside power rails and power distribution network for density scaling

A semiconductor device including a substrate; a continuous buried oxide layer (BOX) formed on the substrate; and a plurality of nanosheet gate-all-round (GAA) device structures on the BOX, wherein a first plurality of stacked gates of the nanosheet GAA device structures are disposed in a logic portion of the substrate and have a first nanosheet width, wherein a second plurality of stacked gates of the nanosheet GAA device structures are disposed in a high density region of the substrate and have a second nanosheet width less than the first nanosheet width, wherein the nanosheet GAA device structures are disposed directly on the continuous buried oxide layer, and wherein a bottom layer of the nanosheet GAA device structures is a bottom gate formed directly on the BOX.

Stacked nanosheet gate-all-around device structures

A semiconductor device includes one or more fins. Each fin includes a top channel portion formed from a channel material, a middle portion, and a bottom substrate portion formed from a same material as an underlying substrate. An oxide layer is formed between the bottom substrate portion of each fin and the isolation layer, with a space between a sidewall of at least a top portion of the isolation dielectric layer and an adjacent sidewall of the one or more fins, above the oxide layer. A gate dielectric, protruding into the space and in contact with the middle portion, is formed over the one or more fins and has a portion formed from a material different from the oxide layer.

Forming a sacrificial liner for dual channel devices

A method for fabricating a semiconductor device includes forming an interfacial layer and a dielectric layer on a base structure and around channels of a first gate-all-around field-effect transistor (GAA FET) device within a first region and a second GAA FET device within a second region, forming at least a scavenging metal layer in the first and second regions, and performing an anneal process after forming at least one cap layer.

Enabling anneal for reliability improvement and multi-Vt with interfacial layer regrowth suppression

A method of providing contact surfaces that includes forming a first mask having an opening to a perimeter of a gate electrode, the first mask having a first protecting portion centrally positioned over the gate electrode within the perimeter, and a second protecting portion of the mask is positioned over metal semiconductor alloy surfaces of source and drain contact surfaces; and recessing exposed portions of metal semiconductor alloy and the gate electrode with an etch. In a following step, the method continues with filling the openings provided by recessing the gate perimeter of the gate electrode, recessing the metal semiconductor alloy adjacent to the gate structure, and the recessed gate electrode adjacent to the metal semiconductor alloy surface of the source and drain contact surfaces with a protecting dielectric material.

Interface-less contacts to source/drain regions and gate electrode over active portion of device

A semiconductor device includes one or more fins. Each fin includes a top channel portion formed from a channel material, and a bottom substrate portion formed from a same material as an underlying substrate. An isolation dielectric layer is formed between and around the bottom substrate portion of the one or more fins. A single oxide layer is formed in direct contact with the bottom substrate portion of each fin, between the bottom substrate portion of each fin and the isolation dielectric layer. A gate dielectric is formed over the one or more fins and between a straight sidewall of at least a top portion of the single oxide layer and an adjacent sidewall of the one or more fins, in contact with both the straight sidewall and the bottom substrate portion.

A semiconductor device is provided that includes a first of a source region and a drain region comprised of a first semiconductor material, wherein an etch stop layer of a second semiconductor material present within the first of the source region and the drain region. A channel semiconductor material is present atop the first of the source region and the drain region. A second of the source and the drain region is present atop the channel semiconductor material. The semiconductor device may be a vertically orientated fin field effect transistor or a vertically orientated tunnel field effect transistor.

Precise junction placement in vertical semiconductor devices using etch stop layers

Embodiments of the invention include first and second devices formed on a substrate. The first device includes a bottom source or drain (S/D) region, a plurality of fins formed on portions of the bottom S/D region, a bottom spacer formed on the bottom S/D region, a dielectric layer, a gate, a top S/D region formed on each fin of a plurality of fins, and one or more contacts. The dielectric layer is disposed between the gate and the fin of the plurality of fins. The second device includes a bottom doped region, a channel formed the bottom doped region, a sidewall doped region of the channel, a gate coupled to the sidewall doped region, a top doped region, and one or more contacts. A junction is formed between the channel and the sidewall doped region. The cap layer is formed on the gate and the top doped region.

Integrating a junction field effect transistor into a vertical field effect transistor

A method of forming a punch through stop region that includes forming isolation regions of a first dielectric material between adjacent fin structures and forming a spacer of a second dielectric material on sidewalls of the fin structure. The first dielectric material of the isolation region may be recessed with an etch process that is selective to the second dielectric material to expose a base sidewall portion of the fin structures. Gas phase doping may introduce a first conductivity type dopant to the base sidewall portion of the fin structure forming a punch through stop region underlying a channel region of the fin structures.

Conformal doping for punch through stopper in fin field effect transistor devices

Integrated chips include a semiconductor fin that has a first active region and a second active region that are electrically separated by an oxide region that completely penetrates the semiconductor fin. A first semiconductor device is formed on the first active region. A second semiconductor device formed on the second active region.

Semiconductor device with mitigated local layout effects

High breakdown voltage devices are provided. In one aspect, a method of forming a device having a VTFET and a LDVTFET includes: forming a LDD in an LDVTFET region; patterning fin(s) in a VTFET region to a depth D1; patterning fin(s) in the LDVTFET region, through the LDD, to a depth D2&#x3e;D1; forming bottom source/drains at a base of the VTFET/LDVTFET fins; burying the VTFET/LDVTFET fins in a gap fill dielectric; recessing the gap fill dielectric to full expose the VTFET fin(s) and partially expose the LDVTFET fin(s); forming bottom spacers directly on the bottom source/drains in the VTFET region and directly on the gap fill dielectric in the LDVTFET region; forming gates alongside the VTFET/LDVTFET fins; forming top spacers above the gates; and forming top source/drains above the top spacers. A one-step fin etch and devices having VTFET and long channel VTFETs are also provided.

Two step fin etch and reveal for VTFETs and high breakdown LDVTFETs

Electrostatic discharge (ESD) devices and methods of manufacture are provided. The method includes forming a plurality of fin structures and a mesa structure from semiconductor material. The method further includes forming an epitaxial material with doped regions on the mesa structure and forming gate material over at least the plurality of fin structures. The method further includes planarizing at least the gate material such that the gate material and the epitaxial material are of a same height. The method further includes forming contacts in electrical connection with respective ones of the doped regions of the epitaxial material.

Electrostatic discharge devices and methods of manufacture

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Glenmont, NY, United States of America

Huiming Bu