International Business Machines Corporation

Elpis Technologies Inc.

Huimei Zhou

Dechao Guo

Miaomiao Wang

Ruilong Xie

Ruqiang Bao

Andrew Mark Greene

Kangguo Cheng

Shogo Mochizuki

Su Chen Fan

Gen Tsutsui

Nicolas J Loubet

Julien Frougier

Michael P Belyansky

Derrick Liu

Peng Xu

Veeraraghavan S Basker

Jingyun Zhang

Huiming Bu

Chih-Chao Yang

Juntao Li

Oleg Gluschenkov

Balasubramanian Pranatharthiharan

Fee Li Lie

Reinaldo Ariel Vega

Baozhen Li

Robert Russell Robison

Richard Anthony Conti

Alexander Reznicek

Chen Zhang

Kisik Choi

Lan Yu

James John Kelly

Yi Song

Ardasheir Rahman

Liying Jiang

Nan Jing

Effendi Leobandung

Junli Wang

Carl John Radens

Chanro Park

Sivananda K Kanakasabapathy

Heng Wu

Zuoguang Liu

Sanjay C Mehta

John Ryan Sporre

Xuefeng Liu

Rajasekhar Venigalla

Ashim Dutta

Gauri V Karve

Stuart A Sieg

Yoo-Mi Lee

Liqiao Qin

A CFET (complementary field effect transistor) structure including a first transistor disposed above a second transistor, a first source/drain region of the first transistor disposed above a second source/drain region of the second transistor, a first source/drain contact for the first source/drain region, and a second source drain contact for the second source drain region. The first source/drain contact is isolated from the second source/drain contact by an L-shaped isolation element including vertical and horizontal isolation elements.

Stacked complementary field effect transistors

A semiconductor device is provided. The semiconductor device includes a semiconductor device comprising: a first stacked field effect transistor (FET) structure in a first device area, the first stacked FET structure comprising a first pull down (PD) transistor, and a first pull up (PU) transistor disposed over the first PD transistor, a first metal gate that is shared by the first PD transistor and the first PU transistor; and an oxygen blocking layer provided on the first metal gate.

Static random access memory device with stacked FETs

An in-situ chip design is provided for self-heating free characterization of a device under test (DUT) with a short time constant. The in-situ chip design includes a pulse generator configured to output a pulse to the DUT and a buffering circuit arranged between the pulse generator and the DUT. The buffering circuit includes a first switch and an adjustable buffer circuit in parallel with the first switch and being controllable to apply one of various degrees of buffering to the pulse.

In-situ chip design for pulse IV self-heating evaluation

Method and resistive structure is provided herein. The resistive structure includes a semiconductor substrate comprising one or more circuit elements and a first interconnect layer disposed on the substrate. The first interconnect layer is between a resistive layer and the semiconductor substrate. A dielectric layer is disposed between the first interconnect layer and the resistive layer. A via extending through the dielectric layer forms an electrical connection between the first interconnect layer and the resistive layer.

Back-end-of-line thin film resistor

Embodiments of the present invention are directed to processing methods and resulting structures for co-integrating gate-all-around (GAA) nanosheets and comb-nanosheets on the same chip, wafer, or substrate. In a non-limiting embodiment of the invention, a GAA nanosheet device is formed in a first region of a substrate. The GAA nanosheet device includes a first nanosheet stack, a second nanosheet stack, and a first fin spacing distance between the first nanosheet stack and the second nanosheet stack. A comb-nanosheet device is formed in a second region of a substrate. The comb-nanosheet device includes a third nanosheet stack, a fourth nanosheet stack, and a second fin spacing distance between the third nanosheet stack and the fourth nanosheet stack that is less than the first fin spacing distance.

Co-integrating gate-all-around nanosheet transistors and comb-nanosheet transistors

Vertically stacked, buried power rails are electrically connected to wrap-around contacts or other electrically conductive liners on transistor source/drain regions. The buried power rails are electrically isolated from each other by an electrical insulator. Wrap-around contacts can be electrically connected to different ones of the vertically stacked, buried power rails or to the same buried power rail.

Semiconductor structure having stacked power rails

A semiconductor device includes a substrate with a planar top surface. At least a first gate cut stressor within a first gate cut region separates a first transistor region from a second transistor region. The first gate cut stressor is directly upon the planar top surface and applies a first tensile force perpendicular to a channel of the first transistor region and perpendicular to a channel of the second transistor region. The tensile force may improve hole and/or electron mobility within a transistor in the first transistor region and within a transistor in the second transistor region. The gate cut stressor may include a lower material within the gate cut region and an upper material upon the lower material. Alternatively, the gate cut stressor may include a liner material that lines the gate cut region and an inner material upon the liner material.

Stressed material within gate cut region

A nanosheet device is provided that has high quality epitaxially grown source/drain regions and reduced parasitic capacitance which are afforded by forming an air gap between an epitaxially grown source/drain region and a semiconductor substrate. The isolation provided by the air gap does not need to extend beneath the channel region of the nanosheet device.

Nanosheet device with air-gaped source/drain regions

A buried power rail is provided in a non-active device region. The buried power rail includes a dielectric liner located on a lower portion of a sidewall and a bottommost surface of the buried power rail. A dielectric cap is located on an upper portion of the sidewall of the buried power rail as well as on a topmost surface of the buried power rail. The dielectric cap is present during the fabrication of a functional gate structure and thus the problems associated with prior art buried power rails are circumvented. The dielectric cap can be removed after the functional gate structure has been formed and a via to buried power rail (VBPR) contact structure can be formed in contact with the buried power rail. In some applications, and after a gate cut process, a gate cut dielectric structure can be formed in contact with the dielectric cap.

Self-aligned buried power rail cap for semiconductor devices

A method of forming stacked vertical field effect devices is provided. The method includes forming a layer stack on a substrate, wherein the layer stack includes a first spacer layer on the substrate, a first protective liner on the first spacer layer, a first gap layer on the first protective liner, a second protective liner on the first gap layer, a second spacer layer on the second protective liner, a sacrificial layer on the second spacer layer, a third spacer layer on the sacrificial layer, a third protective liner on the third spacer layer, a second gap layer on the third protective liner, a fourth protective liner on the second gap layer, and a fourth spacer layer on the fourth protective liner. The method further includes forming channels through the layer stack, a liner layer on the sidewalls of the channels, and a vertical pillar in the channels.

Three-dimensional field effect device

In one embodiment a semiconductor structure comprises a semiconductor substrate, a trench dielectric layer disposed in a trench of the semiconductor substrate, a first source/drain region disposed in contact with the semiconductor substrate, a gate and a second source/drain region. The gate is disposed between the first source/drain region and the second source/drain region. The semiconductor structure further comprises a dielectric isolation layer disposed between the semiconductor substrate and the second source/drain region.

Electrostatic discharge diode having dielectric isolation layer

Semiconductor devices and methods of forming the same include a first device region, a second device region, and an inter-device dielectric spacer between the first device region and the second device region. The first device region includes a first device channel, a first-polarity work function metal layer on the first device channel, and a second-polarity work function metal layer on the first device channel. The second device region include a second device channel, and a second-polarity work function metal layer on the second device channel.

Nanosheet transistors with self-aligned gate cut

Semiconductor devices and methods of forming the same include forming dummy gate spacers in a trench in a semiconductor substrate. A dummy gate is formed in the trench. An exposed dummy gate spacer is replaced with a sacrificial spacer. A cap layer is formed over the dummy gate. The cap layer is etched to expose the dummy gate. The sacrificial spacer is replaced with an isolation dielectric spacer. The dummy gate is replaced with a conductor.

Self-aligned gate contact for VTFETs

An approach for creating a buried local interconnect around a DDB (double diffusion break) to reduce parasitic capacitance on a semiconductor device is disclosed. The approach utilizes a metal, as the local interconnect, buried in a cavity around the DDB region of a semiconductor substrate. The metal is disposed by two dielectric layers and the substrate. The two dielectric layers are recessed beneath two gate spacers. The buried local interconnect is recessed into the cavity where the top surface of the interconnect is situated below the top surface of the surrounding S/D (source/drain) epi (epitaxy). The metal of the local interconnect can be made from W, Ru or Co.

Recessed local interconnect formed over self-aligned double diffusion break

A metal-insulator-metal (MIM) capacitor structure includes a substrate extending along a first direction to define a length, a second direction orthogonal to the first direction to define a width, and a third direction orthogonal to the first and second direction to define a height. The substrate includes a first capacitance region and a second capacitance region. The first capacitance region has a first maximum operating voltage (Vmax) and the second capacitance region has a second Vmax that is greater than the first Vmax.

Metal-insulator-metal capacitor structure supporting different voltage applications

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Albany, NY, United States of America

Huimei Zhou