Chinese Academy of Sciences

Beijing Superstring Academy of Memory Technology

Huilong Zhu

Weixing Huang

Qi Wang

The present invention relates to a semiconductor memory cell structure, a semiconductor memory as well as preparation method and application thereof. The semiconductor memory cell structure includes: a substrate; and a first transistor layer, an isolation layer and a second transistor layer. The first transistor layer includes a first stack structure formed by stacking a first source, a first channel, and a first drain from bottom to top; and a first gate located on a sidewall of the first stack structure. The second transistor layer includes: a second stack structure formed by stacking a second drain, a second channel, and a second source from bottom to top; and a second gate located on a sidewall of the second stack structure, at least a part of a sidewall of the second drain is in direct contact with the first gate. The present invention provides a 2T0C type DRAM cell with an improved structure, has the advantages of vertical stack integration, high integration level, low leakage current, short refresh time and the like, and is significantly superior to the existing 2T0C type DRAM.

Semiconductor memory cell structure, semiconductor memory, preparation method and application thereof

A semiconductor device, including a substrate, a first electrode layer, a functional layer, and a second electrode layer. The functional layer is located between the first electrode layer and the second electrode layer, and includes a first region and a second region having a C-shaped structure surrounding the first region. The C-shape structure opens toward a direction that is parallel with the substrate and away from the first region, that is, the C-shaped structure opens toward a distal side. The first region is made of at least germanium, and the second region includes a C-shaped ferroelectric layer and a C-shaped gate that are sequentially stacked. The C-shaped ferroelectric layer serves as a memory layer of the memory device.

Semiconductor device having ferroelectric layer in recess and method for manufacturing the same

A semiconductor device and a method for manufacturing the same. A first electrode layer, a semiconductor layer, and a second electrode layer are formed on a substrate. The semiconductor layer is etched form a sidewall to form a cavity. A channel layer is formed at the cavity and sidewalls of the first electrode layer and the second electrode layer. The channel layer includes a first channel part located in the cavity and a second channel part located outside the cavity. The first channel part is filled with a dummy gate layer. The dummy gate layer is etched from a sidewall. The second channel part and the first channel part, which is in contact with upper and lower surfaces of the dummy gate layer are removed to form a recess. The recess is filled with a dielectric material to form an isolation sidewall.

Growing community of inventors

Beijing, China

Huilong Zhu