Taiwan Semiconductor Manufacturing Comp. Ltd.

Huiling Shang

Xusheng Wu

Chang-Miao Liu

Ying-Keung Leung

Youbo Lin

Ko-Cheng Liu

A method includes forming a semiconductor fin protruding from a substrate, forming a cladding layer on sidewalls of the semiconductor fin, forming first and second dielectric fins sandwiching the semiconductor fin, and removing the cladding layer. The removal of the cladding layer forms trenches between the semiconductor fin and the first and second dielectric fins. After the removing of the cladding layer, a dummy gate structure is formed over the semiconductor fin and in the trenches. The method also includes recessing the semiconductor fin in a region proximal to the dummy gate structure, forming an epitaxial feature on the recessed semiconductor fin, and forming a metal gate stack replacing the dummy gate structure. A top surface of the recessed semiconductor fin in the region has a concave shape.

Multi-gate device including semiconductor fin between dielectric fins and method of fabrication thereof

A semiconductor structure includes a substrate, an oxide layer disposed over the substrate, a stack of semiconductor layers disposed over the oxide layer, and an epitaxial source/drain (S/D) feature disposed adjacent to the stack of semiconductor layers. A portion of the epitaxial S/D feature is horizontally surrounded by the oxide layer.

Isolation structures in multi-gate semiconductor devices and methods of fabricating the same

Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises first semiconductor stack over a substrate, wherein the first semiconductor stack includes first semiconductor layers separated from each other and stacked up along a direction substantially perpendicular to a top surface of the substrate; second semiconductor stack over the substrate, wherein the second semiconductor stack includes second semiconductor layers separated from each other and stacked up along the direction substantially perpendicular to the top surface of the substrate; inner spacers between edge portions of the first semiconductor layers and between edge portions of the second semiconductor layers; and a bulk source/drain (S/D) feature between the first semiconductor stack and the second semiconductor stack, wherein the bulk S/D feature is separated from the substrate by a first air gap, and the bulk S/D feature is separated from the inner spacers by second air gaps.

Semiconductor device with S/D bottom isolation and methods of forming the same

A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a gate stack over the substrate. The semiconductor device structure also includes a spacer element over a sidewall of the gate stack. The spacer element is doped with a dopant, and the dopant reduces a dielectric constant of the spacer element. The spacer element has a first atomic concentration of the dopant near an inner surface of the spacer element adjacent to the gate stack. The spacer element has a second atomic concentration of the dopant near an outer surface of the spacer element. The first atomic concentration of the dopant is different than the second atomic concentration of the dopant.

Semiconductor device structure with metal gate stack

A method includes forming a semiconductor substrate having an oxide layer embedded therein, forming a multi-layer (ML) stack including alternating channel layers and non-channel layers over the semiconductor substrate, forming a dummy gate stack over the ML, forming an S/D recess in the ML to expose the oxide layer, forming an epitaxial S/D feature in the S/D recess, removing the non-channel layers from the ML to form openings between the channel layers, where the openings are formed adjacent to the epitaxial S/D feature, and forming a high-k metal gate stack (HKMG) in the openings between the channel layers and in place of the dummy gate stack.

A method including providing a device including a gate structure and a source/drain feature adjacent to the gate structure. An insulating layer (e.g., CESL, ILD) is formed over the source/drain feature. A trench is etched in the insulating layer to expose a surface of the source/drain feature. A semiconductor material is then formed in the etched trench on the surface of the source/drain feature. The semiconductor material is converted to a silicide.

Semiconductor device having contact feature and method of fabricating the same

A semiconductor device and a method of forming the same are provided. A semiconductor device of the present disclosure includes a first fin including a first source/drain region, a second fin including a second source/drain region, a first isolation layer disposed between the first source/drain region and the second source/drain region, and a second isolation layer disposed over the first isolation layer. A first portion of the first isolation layer is disposed on sidewalls of the first source/drain region and a second portion of the first isolation layer is disposed on sidewalls of the second source/drain region. A portion of the second isolation layer is disposed between the first portion and second portion of the first isolation layer.

Devices with strained isolation features

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a metal gate stack over the semiconductor substrate. The semiconductor device structure also includes a spacer element over a sidewall of the metal gate stack. The spacer element is doped with a dopant, and the dopant reduces a dielectric constant of the spacer element. An atomic concentration of the dopant decreases along a direction from an inner surface of the spacer element adjacent to the metal gate stack towards an outer surface of the spacer element.

A semiconductor structure includes a semiconductor substrate, an oxide layer disposed over the semiconductor substrate, a high-k metal gate structure (HKMG) interleaved with the stack of semiconductor layers, and an epitaxial source/drain (S/D) feature disposed adjacent to the HKMG, wherein a bottom portion of the epitaxial S/D feature is defined by the oxide layer.

Examples of an integrated circuit with a strain-generating liner and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, and a gate disposed on the fin. The gate has a bottom portion disposed towards the fin and a top portion disposed on the bottom portion. A liner is disposed on a side surface of the bottom portion of the gate such that the top portion of the gate is free of the liner. In some such examples, the liner is configured to produce a channel strain.

Integrated circuits with channel-strain liner

Integrated circuit devices and methods of forming the same are provided. An integrated circuit device in an embodiment includes a first multi-gate active region over a substrate, a second multi-gate active region over the substrate, a first gate structure over the first multi-gate active region, a second gate structure over the second multi-gate active region, and a dielectric feature disposed between the first gate structure and the second gate structure. The dielectric feature includes an oxygen-free layer in contact with the first gate structure and the second gate structure, a silicon oxide layer over the oxygen-free layer, and a transition layer disposed between the oxygen-free layer and the silicon oxide layer. An oxygen content of the transition layer is smaller than an oxygen content of the silicon oxide layer.

Gate cut dielectric feature and method of forming the same

Aspects of the disclosure provide a method for fabricating a semiconductor device. A pre-stress liner is formed over a structure. The structure includes a gate structure having sidewalls. A protection layer is formed. The protection layer covers a first portion of the pre-stress liner that extends along the sidewalls of the gate structure, and exposes a second portion of the pre-stress liner that is away from the sidewalls of the gate structure. An oxygen-containing layer is formed. The oxygen-containing layer covers the pre-stress liner and the protection layer. The oxygen-containing layer is separated from the first portion of the pre-stress liner by the protection layer. The structure is annealed such that the second portion of the pre-stress liner oxidizes by receiving oxygen from the oxygen-containing layer, while the first portion of the pre-stress liner remains unoxidized due to the protection layer.

Semiconductor device with air spacer and stress liner

A structure and a formation method of a semiconductor device are provided. The method includes forming a dummy gate stack over a semiconductor substrate. The dummy gate stack has a dummy gate electrode and a dummy gate dielectric layer. The method also includes forming spacer elements over sidewalls of the dummy gate stack and partially removing the dummy gate electrode to form a recess. The method further includes partially removing the spacer elements to enlarge the recess and removing a remaining portion of the dummy gate electrode to expose the dummy gate dielectric layer. In addition, the method includes doping the spacer elements after the remaining portion of the dummy gate electrode is removed and removing the dummy gate dielectric layer. The method further includes forming a metal gate stack in the recess.

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Hsinchu County, Taiwan

Huiling Shang