Huawei Technologies Co., Limited

HuiLi Fu

Shujie Cai

Xiaodong Zhang

Nan Zhao

Liangsheng Liu

Jyh Rong Lin

Xinhong Li

Xiao Liang Hu

Xing Fu

Zhiqiang Ma

Jianwei Guo

Shanghsuan Chiang

Tewei Chen

Song Gao

Junlei Tao

Wenxu Xie

Feiyu Luo

Xiangxiong Zhang

Tiejun Liu

The present invention provides a chip integration module, including a die, a passive device, and a connecting piece, where the die is provided with a die bonding portion, the passive device is provided with a passive device bonding portion, the die bonding portion of the die and the passive device bonding portion of the passive device are disposed opposite to each other, and the connecting piece is disposed between the die bonding portion and the passive device bonding portion and is connected to the die bonding portion and the passive device bonding portion. The chip integration module of the present invention achieves easy integration and has low costs. Moreover, a path connecting the die to the passive device becomes shorter, which can improve performance of the passive device. The present invention further discloses a chip package structure and a chip integration method.

Chip integration module, chip package structure, and chip integration method

A chip and a packaging method thereof. In the chip, first solder pads in a first solder pad array on a first substrate are attached to corresponding second pins in second pin arrays on different dies to implement short-distance and high-density interconnection of the different dies. A molding body is used to wrap a first pin, a second pin, a first solder pad, and the first substrate, so that a fan-out unit and the first substrate are molded into an integral structure. In the integral structure, bottoms of first pins that are in a first pin array on a die and that are electrically connected to a periphery of the chip are not wrapped by the molding body.

Encapsulation of a substrate electrically connected to a plurality of pin arrays

A patch antenna unit includes a first support layer, a substrate, a second support layer, and an integrated circuit that are stacked. One radiation patch is attached to the first support layer, and one radiation patch is attached to the second support layer. A ground layer is disposed on the second support layer, a coupling slot is disposed on the ground layer, and a feeder corresponding to the coupling slot is disposed on the second support layer. The integrated circuit is connected to the first ground layer and the feeder. In the foregoing specific technical solution, a four-layer substrate is used for fabrication.

Patch antenna unit and antenna

A chip package structure, including a substrate, multiple chips and multiple discrete devices that are packaged on an upper surface of the substrate, and a heat dissipation apparatus, where the heat dissipation apparatus includes an insulation layer and a thermally conductive layer that are laminated. The insulation layer completely encloses and adheres to outer surfaces of the multiple chips, outer surfaces of the multiple discrete devices, and the upper surface of the substrate and configured to conduct heat generated by the multiple chips and the multiple discrete devices to the thermally conductive layer and the substrate such that the heat generated by the multiple chips and the multiple discrete devices dissipated using the thermally conductive layer and the substrate.

Chip package structure and manufacturing method thereof

An apparatus includes a circuit device, a heat sink fin, and a thermal interface material layer. The thermal interface material layer is thermally coupled to the circuit device and the heat sink fin. The thermal interface material layer includes a first alloy layer, a nanometal particle layer, and a second alloy layer. The first alloy layer is thermally coupled to the circuit device. The nanometal particle layer is thermally coupled to the first alloy layer. The nanometal particle layer includes nanometal particles and an intermediate mixture.

Apparatus and manufacturing method

A patch antenna unit and an antenna that relate to the field of communications technology wherein the patch antenna unit includes a first support layer, a substrate, a second support layer, and an integrated circuit that are stacked. One radiation patch is attached to the first support layer, and one radiation patch is attached to the second support layer. A ground layer is disposed on the second support layer, a coupling slot is disposed on the ground layer, and a feeder corresponding to the coupling slot is disposed on the second support layer. The integrated circuit is connected to the first ground layer and the feeder. In the foregoing specific technical solution, a four-layer substrate is used for fabrication.

The present invention provide an IC die, including an underlay; an active component; an interconnection layer, covering the active component, where the interconnection layer includes multiple metal layers and multiple dielectric layers, the multiple metal layers and the multiple dielectric layers are alternately arranged, a metal layer whose distance to the active component is the farthest in the multiple metal layers includes metal cabling and a metal welding pad; and a heat dissipation layer, where the heat dissipation layer covers a region above the interconnection layer except a position corresponding to the metal welding pad, the heat dissipation layer is located under a package layer, the package layer includes a plastic packaging material, and the heat dissipation layer includes an electrical-insulating material whose heat conductivity is greater than a preset value.

Integrated circuit die and manufacture method thereof

The present embodiments provides a chip, including a carrier, a redistribution structure, and multiple packaging function modules, where the multiple packaging function modules each have at least a part wrapped by a colloid, and are fastened to the redistribution structure side by side; the redistribution structure is fastened to the carrier, and the redistribution structure includes one or more redistribution metal layers; the redistribution metal layer communicatively connects the multiple packaging function modules and the carrier. The redistribution structure further includes one or more interconnect metal layers, and the interconnect metal layer is communicatively connected to at least two packaging function modules so as to provide a signal path between the at least two packaging function modules. In the chip, two packaging function modules are placed on the carrier side by side, and a signal path is established between the two packaging function modules by using the redistribution structure.

Chip

A conical inductor provided in the present invention includes: a housing, a conical coil located inside the housing, a first pin and a second pin respectively connected to two ends of the conical coil, where one end of the first pin is connected to one end of the conical coil, the other end of the first pin is connected to a hole in a first side wall of the housing in a fastened manner, one end of the second pin is connected to the other end of the conical inductor, and the other end of the second pin is connected to a hole in a second side wall of the housing in a fastened manner; and each of the first pin and the second pin includes one segment of waveform segment fluctuating in a direction perpendicular to a top wall of the housing.

Conical inductor, printed circuit board, and optical module

A chip stacked package structure includes a first chip and a second chip, where the second chip is stacked with the first chip and the second chip includes a package layer and a first routing layer, where the package layer includes at least two dies and an attaching part configured to attach the at least two dies, where the attaching part is provided with multiple vias, with a part of vias in the multiple vias disposed at an outer periphery of the at least two dies, and the other part of vias in the multiple vias disposed between the at least two dies, and the first routing layer electrically connects the at least two dies; where the package layer is located between the first routing layer and the first chip, an electrically conductive material is provided in the multiple vias.

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Shenzhen, China

HuiLi Fu