Taiwan Semiconductor Manufacturing Comp. Ltd.

Huicheng Chang

Yee-Chia Yeo

Liang-Yin Chen

Su-Hao Liu

Kuo-Ju Chen

Chun-Feng Nieh

Li-Ting Wang

Chia-Cheng Chen

Yu-Chang Lin

Wei-Ting Chien

Szu-Ying Chen

Chun-Hung Wu

Wen-Yen Chen

Sen-Hong Syue

Ying-Lang Wang

Jyh-Cherng Sheu

Lun-Kuang Tan

Teng-Chun Tsai

Tsan-Chun Wang

Cheng-Tung Lin

Hung-Ta Lin

Chi-Yuan Chen

Syun-Ming Jang Jang

Weng Chang

Hou-Yu Chen

Mrunal Abhijith Khaderbad

Yi-Fan Chen

Kei-Wei Chen

Ziwei Fang

Xiong-Fei Yu

Chih-Kai Yang

Wei-Ming You

Cheng-Po Chau

Chih-Wei Chang

Huai-Tei Yang

Che-Hao Chang

Chun-Yen Peng

Yan-Ming Tsai

Hong-Mao Lee

Keng-Chu Lin

Tsung-Lin Lee

Chun-Hsiung Lin

Chien-Hao Chen

Pang-Yen Tsai

Ching-Hwanq Su

Wei-Jung Lin

Chang-Miao Liu

Ya Hui Chang

Huang-Yi Huang

Yu-Tien Shen

Li-Chieh Wu

Chia-Ling Chan

Kuo-Hsiu Wei

Chia-Han Lai

Ting-Kui Chang

Kuo-Cheng Ching

Tze-Liang Lee

Da-Yuan Lee

Chun-Hsien Huang

Kai-Hsuan Lee

Jr-Hung Li

Chia-Ching Lee

Chien-Tai Chan

Hsueh Wen Tsau

Chih-Chang Hung

Kuo-Yin Lin

Chih-Pin Tsao

I-Hsieh Wong

Cheng-Yu Yang

Tsai-Jung Ho

Hsiao-Kuan Wei

Pei-Yu Chou

Ru-Gun Liu

Carlos H Diaz

Shi Ning Ju

Tai-Chun Huang

Jyu-Horng Shieh

Mao-Lin Huang

Yung-Sung Yen

Wei-Liang Lin

Chun-Yen Chang

Yi-Nien Su

Chien-Hsun Wang

Bo-Cyuan Lu

Wei-Yip Loh

Hung-Hsu Chen

Yahru Cheng

Shu-Huei Suen

Ya-Wen Yeh

Chih-Hao Wang

Ching-Wei Tsai

Chun-Sheng Liang

Chih-Hung Chen

Da-Wen Lin

Jeff J Xu

Wan-Yi Kao

Ming-Chyi Liu

Chi-On Chui

Hui-Chi Huang

Wen-Kai Lin

A method includes: transporting a wafer to an apparatus, the apparatus including: a first chamber configured to receive the wafer and a first gas; a second chamber surrounding the first chamber and configured to receive a second gas; a plurality of gas inlets on a chamber wall of the second chamber; and a plurality of gas vents on the chamber wall of the second chamber; heating the first chamber while keeping a gas pressure difference between the first chamber and the second chamber within a tolerance limit; and cooling the first chamber by exchanging the second gas in the second chamber while keeping the gas pressure difference within the tolerance limit.

Annealing apparatus and method of operating the same

A method of forming a semiconductor device includes forming a first dummy gate structure over a first region of a substrate and a second dummy gate structure over a second region of the substrate, the first region and the second region of the substrate having a first composition, the first composition having a first etch rate; implanting the first region of the substrate with dopants laterally adjacent to the first dummy gate structure, wherein after the implanting the first region, the first region has a second composition having a second etch rate, the second etch rate being different from the first etch rate; etching a first recess in the first region of the substrate having the second composition and a second recess in the second region having the first composition; and epitaxially growing a first source/drain region in the first recess and a second source/drain region in the second recess.

Semiconductor device and methods of forming the same

A semiconductor device and a method of forming the same are provided. The method includes forming a semiconductor fin extending from a substrate. A dummy gate stack is formed over the semiconductor fin. The dummy gate stack extends along sidewalls and a top surface of the semiconductor fin. The semiconductor fin is patterned to form a recess in the semiconductor fin. A semiconductor material is deposited in the recess. An implantation process is performed on the semiconductor material. The implantation process includes implanting first implants into the semiconductor material and implanting second implants into the semiconductor material. The first implants have a first implantation energy. The second implants have a second implantation energy different from the first implantation energy.

Method of manufacturing a source/drain of a semiconductor device using multiple implantation processes

A method includes forming a first plurality of fins in a first region of a substrate, a first recess being interposed between adjacent fins in the first region of the substrate, the first recess having a first depth and a first width, forming a second plurality of fins in a second region of the substrate, a second recess being interposed between adjacent fins in the second region of the substrate, the second recess having a second depth and a second width, the second width of the second recess being less than the first width of the first recess, the second depth of the second recess being less than the first depth of the first recess, forming a first dielectric layer in the first recess and the second recess, and converting the first dielectric layer in the first recess and the second recess to a treated dielectric layer.

Shallow trench isolation forming method and structures resulting therefrom

A method includes forming a first protruding fin and a second protruding fin over a base structure, with a trench located between the first protruding fin and the second protruding fin, depositing a trench-filling material extending into the trench, and performing a laser reflow process on the trench-filling material. In the reflow process, the trench-filling material has a temperature higher than a first melting point of the trench-filling material, and lower than a second melting point of the first protruding fin and the second protruding fin. After the laser reflow process, the trench-filling material is solidified. The method further includes patterning the trench-filling material, with a remaining portion of the trench-filling material forming a part of a gate stack, and forming a source/drain region on a side of the gate stack.

Trench filling through reflowing filling material

A method includes mounting a first wafer on a first wafer chuck and mounting a second wafer on a second wafer chuck. The second wafer is brought into physical contact with the first wafer. A relative distance between the first wafer and the second wafer is monitored using a distance sensor. A pressure of a vacuum zone on the second wafer chuck is controlled using feedback from the distance sensor. The bonded first wafer and second wafer are removed from the first wafer chuck.

Bonding system and method for using the same

A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.

Device having an air gap adjacent to a contact plug and covered by a doped dielectric layer

In an embodiment, a device includes: a source/drain region adjacent a channel region; an inter-layer dielectric on the source/drain region; a source/drain contact extending through the inter-layer dielectric and into the source/drain region; a metal-semiconductor alloy region between the source/drain contact and the source/drain region, the metal-semiconductor alloy region disposed beneath a top surface of the channel region, the metal-semiconductor alloy region including a first dopant; and a contact spacer around the source/drain contact, the contact spacer including the first dopant and an amorphizing impurity.

Transistor source/drain contacts and methods of forming the same

A method includes forming a fin structure over a substrate; depositing a dummy gate layer over the substrate and the fin structure; depositing a hard mask stack over the dummy gate layer; depositing a photoresist bottom layer over the hard mask stack, wherein the photoresist bottom layer has a first stress; performing an implantation process to the photoresist bottom layer to form an implanted bottom layer with a second stress closer to 0 than the first stress; patterning the implanted bottom layer; patterning the hard mask stack and the dummy gate layer by using the patterned implanted bottom layer as an etch mask to form a dummy gate structure over the fin structure; and replacing the dummy gate structure with a metal gate structure.

Method for manufacturing semiconductor device

In an embodiment, a method includes: etching a trench in a substrate; depositing a liner material in the trench with an atomic layer deposition process; depositing a flowable material on the liner material and in the trench with a contouring flowable chemical vapor deposition process; converting the liner material and the flowable material to a solid insulation material, a portion of the trench remaining unfilled by the solid insulation material; and forming a hybrid fin in the portion of the trench unfilled by the solid insulation material.

Transistor isolation regions and methods of forming the same

A semiconductor device and a method of forming the same are provided. A method includes forming a fin structure on a substrate. The fin structure includes a plurality of first nanostructures and a plurality of second nanostructures alternately stacked. A dummy gate is formed along sidewalls and a top surface of the fin structure. A portion of the fin structure exposed by the dummy gate is recessed to form a first recess. An epitaxial source/drain region is formed in the first recess. Dopant atoms within the epitaxial source/drain region are driven into the plurality of second nanostructures. The dummy gate and the plurality of first nanostructures are removed. A replacement gate is formed wrapping around the plurality of second nanostructures.

Nanostructure FET and method of forming same

A method of forming a semiconductor device is provided. The method includes providing a substrate having a first region and a second region; forming a plurality of trenches in the first region of the substrate; forming a multi-layer stack over the substrate and in the trenches; and patterning the multi-layer stack and the substrate to form first nanostructures over first fins in the first region and second nanostructures over second fins in the second region, where the multi-layer stack includes at least one of first semiconductor layers and at least one of second semiconductor layer stacked alternately, and the plurality of trenches are in corresponding ones of the first fins.

Methods of forming alignment structure with trenches for semiconductor devices

A temperature measuring apparatus for measuring a temperature of a substrate is described. A light emitting source that emits light signals such as laser pulses are applied to the substrate. A detector on the other side of the light emitting source receives the reflected laser pulses. The detector further receives emission signals associated with temperature or energy density that is radiated from the surface of the substrate. The temperature measuring apparatus determines the temperature of the substrate during a thermal process using the received laser pulses and the emission signals. To improve the signal to noise ratio of the reflected laser pulses, a polarizer may be used to polarize the laser pulses to have a S polarization. The angle in which the polarized laser pulses are applied towards the substrate may also be controlled to enhance the signal to noise ratio at the detector's end.

Apparatus, system, and method for measuring the temperature of a substrate

A method includes forming a semiconductor fin protruding over a substrate; forming an isolation structure over the substrate; depositing a first metal oxide layer over the isolation structure; depositing a first oxide layer over the first metal oxide layer; depositing a second metal oxide layer over the first oxide layer, in which the first metal oxide layer and the second metal oxide layer comprise amorphous structures; performing a chemical mechanism polishing (CMP) process to the first metal oxide layer, the first oxide layer, and the second metal oxide layer; after the CMP process is completed, performing an annealing process such that the first metal oxide layer and the second metal oxide layer are transferred from the amorphous structures into crystalline structures; forming a gate structure over the semiconductor fin; and forming source/drain structures over the substrate and on opposite sides of the gate structure.

Method for forming semiconductor device with monoclinic crystalline metal oxide capping layer

In an embodiment, a method includes: placing a wafer on an implanter platen, the wafer including integrated circuit dies; measuring a position of the wafer by measuring a position of an outer edge of the integrated circuit dies with a camera; determining an angular displacement between the position of the wafer and a reference position of the wafer; and rotating the implanter platen by the angular displacement.

Wafer positioning method and apparatus

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Tainan, Taiwan

Huicheng Chang