Nan Ya Technology Corporation

N&auml;naya Technology Corporation

Hui Min Mao

Tzu-Ching Tsai

Yi-Nan Chen

Ying Huan Chuang

Hsien-Wen Liu

Yi-Chen Chen

Tien-Sung Chen

Yu-Pi Lee

Tzu Ching Tsai

Han Chih Lin

Shih-Chieh Kao

A process for measuring depth of a source and drain of a MOS transistor. The MOS transistor is formed on a semiconductor substrate on which a trench capacitor is formed and a buried strap is formed between the MOS transistor and the trench capacitor. The process includes the following steps. First, resistances of the buried strap at a plurality of different depths are measured. Next, a curve correlating the resistances with the depths is established. Next, slopes of the resistance to the depth for the curve are obtained. Finally, a depth corresponding to a minimum resistance before the slope of the resistance to the depth reaches to zero is obtained.

Process for measuring depth of source and drain

A method of metal etching post cleaning. A substrate with a surface covered by a patterned metal layer and a patterned resist layer in order is provided, subsequently, oxygen-plasma ashing is performed to remove the patterned resist layer to expose the surface of the patterned metal layer. Next, an ozone-plasma ashing is performed to release charges on the surface of the patterned metal layer, the ozone-plasma ashing time at 30 sec&tilde;180 sec, and the ozone-plasma ashing temperature at 200&deg; C.&tilde;300&deg; C. The surface of the patterned metal layer is finally cleaned with sulfuric peroxide, molar concentration of sulfuric acid and hydrogen peroxide therein being 0.07M&tilde;0.4M and 0.8M&tilde;1.5M, respectively. In addition, the temperature of the sulfuric peroxide during post cleaning is 25&deg; C.&tilde;50&deg; C.

Method of metal etching post cleaning

A method of fabricating shallow trench isolation. In the method, a refill step of oxide layer and a step of forming a sacrificial layer on the semiconductor substrate are applied after filling insulating layer into the shallow trenches. The purpose of the steps is to protect the oxide layer on the semiconductor substrate and the corner of the shallow trenches, used to isolate the STI.

Method of fabricating shallow trench isolation

A method of forming inter-metal dielectric (IMD). A substrate having a patterned metal layer thereon has at least one opening to expose the substrate. The opening has an aspect ratio of 3.5&tilde;4.5. Next, the opening is filled with a first dielectric layer, and voids are formed in the upper portion of the first dielectric layer due to the high aspect ratio opening. Thereafter, the first dielectric layer is etched to leave the first dielectric layer with a predetermined height in the opening without voids. Finally, a second dielectric layer is formed on the first dielectric layer to completely fill the opening.

Method of forming inter-metal dielectric

Method for forming buried plates. The method includes providing a substrate formed with a pad stacked layer on the surface, a bottle trench and a protective layer on the upper sidewalls of the bottle trench, forming a doped hemispherical silicon grain (HSG) layer on the protective layer and the sidewalls and bottom of the bottle trench, removing the hemispherical silicon grain layer on the protective layer without removing the hemispherical silicon grain layer from the lower sidewalls and bottom of the bottle trench, forming a covering layer on the protective layer, and subjecting the doped hemispherical silicon grain layer to drive-in annealing so that ions in the HSG layer diffuse out to the substrate, thereby forming a buried plate within the lower sidewalls of the bottle trench.

Method for forming buried plates

A method for estimating capacitance of deep trench capacitor in a substrate. After a photoresist layer used to define the region of the lower electrode is formed on an oxide layer doping with a conducting type dopant, the height difference of the photoresist layer between the memory cell array area and the supporting area is measured. The radicand of the height difference is directly proportional to a capacitance of a capacitor to-be-formed in the trenches.

Method for estimating capacitance of deep trench capacitors

A method of improving planarity of a photoresist. Before coating the photoresist over a silicon oxide layer, modifying a surface of the silicon oxide layer to enhance an adhesion between the silicon oxide layer and the photoresist. The photoresist flows into trenches of the silicon oxide layer, then the photoresist has good planarity, even after performing a baking process.

Growing community of inventors

Tainan Hsien, Taiwan

Hui Min Mao