Taiwan Semiconductor Manufacturing Comp. Ltd.

Hui-Min Huang

Ming-Da Cheng

Chung-Shi Liu

Chih-Wei Lin

Wei-Hung Lin

Meng-Tse Chen

Chen-Hua Douglas Yu

Chang-Jung Hsueh

Chih-Fan Huang

Tsai-Tsung Tsai

Wen-Hsiung Lu

Yu-Peng Tsai

Yung-Sheng Lin

Wan-Yu Chiang

Chen-Shien Chen

Mirng-Ji Lii

Yu-Chih Liu

Hsuan-Ting Kuo

Ai-Tee Ang

Jing Ruei Lu

Kai-Jun Zhan

Tsung-Chih Chien

Kai Jun Zhan

Hao-Yi Tsai

Tin-Hao Kuo

Hsiu-Jen Lin

Shy-Jay Lin

Burn Jeng Lin

Chun-Cheng Lin

Kuei-Wei Huang

Kuo-Ching Hsu

Jaw-Jung Shin

Kuo-Lung Pan

Shing-Chao Chen

Wei-Sen Chang

Shih-Chi Wang

Ming-Fa Chen

Tien-I Bao

Po-Hao Tsai

Sung-Feng Yeh

Chien Ling Hwang

Chih Wei Lu

Cheng-Ting Chen

Bor-Ping Jang

Hao-Jan Pei

Yen-Chang Hu

Chen-En Yen

Hsu-Lun Liu

Shou-Cheng Hu

Cheng-Jen Lin

Chin-Wei Kang

Kuan-Liang Lai

Chien-Chun Wang

Cheng-Tar Wu

Chih-Chun Chiu

Mirng-ji Lii

Wei-hung Lin

A chip structure is provided. The chip structure includes a substrate. The chip structure includes a first conductive line over the substrate. The chip structure includes an insulating layer over the substrate and the first conductive line. The chip structure includes a conductive pillar over the insulating layer. The chip structure includes a solder bump on the conductive pillar. The solder bump is in direct contact with the conductive pillar.

Chip structure and method for forming the same

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first conductive structure over the semiconductor substrate. The first conductive structure has a first protruding portion extending towards the semiconductor substrate from a lower surface of the first conductive structure. The semiconductor device structure also includes a second conductive structure over the semiconductor substrate. The second conductive structure is substantially as wide as the first conductive structure, and the second conductive structure has a second protruding portion extending towards the semiconductor substrate from a lower surface of the second conductive structure. The first conductive structure is closer to a center point of the semiconductor substrate than the second conductive structure. The second protruding portion is wider than the first protruding portion, and bottoms of the first protruding portion and the second protruding portion are substantially level with each other.

Semiconductor device structure with conductive bumps

A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die are encapsulated such that the encapsulant is thicker than the first die and the second die, and vias are formed within the openings. A redistribution layer can also be formed to extend over the encapsulant, and the first die may be separated from the second die.

Semiconductor package system and method

A semiconductor die including mechanical-stress-resistant bump structures is provided. The semiconductor die includes dielectric material layers embedding metal interconnect structures, a connection pad-and-via structure, and a bump structure including a bump via portion and a bonding bump portion. The entirety of a bottom surface of the bump via portion is located within an area of a horizontal top surface of a pad portion of the connection pad-and-via structure.

Semiconductor die including stress-resistant bonding structures and methods of forming the same

Provided are a package structure and a method of forming the same. The method includes providing a first package having a plurality of first dies and a plurality of second dies therein; performing a first sawing process to cut the first package into a plurality of second packages, wherein one of the plurality of second packages comprises three first dies and one second die; and performing a second sawing process to remove the second die of the one of the plurality of second packages, so that a cut second package is formed into a polygonal structure with the number of nodes greater than or equal to 5.

Package structure and method of forming the same

Package structure

A method includes forming a reconstructed package substrate, which includes placing a plurality of substrate blocks over a carrier, encapsulating the plurality of substrate blocks in an encapsulant, planarizing the encapsulant and the plurality of substrate blocks to reveal redistribution lines in the plurality of substrate blocks, and forming a redistribution structure overlapping both of the plurality of substrate blocks and encapsulant. A package component is bonded over the reconstructed package substrate.

Packages including multiple encapsulated substrate blocks and overlapping redistribution structures

A chip structure is provided. The chip structure includes a substrate. The chip structure includes a first conductive line over the substrate. The chip structure includes an insulating layer over the substrate and the first conductive line. The chip structure includes a conductive pillar over the insulating layer. The conductive pillar is formed in one piece, the conductive pillar has a lower surface, a protruding connecting portion, and a protruding locking portion, the protruding connecting portion protrudes from the lower surface and passes through the insulating layer and is in direct contact with the first conductive line, the protruding locking portion protrudes from the lower surface and is embedded in the insulating layer. The chip structure includes a solder bump on the conductive pillar. The solder bump is in direct contact with the conductive pillar.

An embodiment is method including forming a first die package over a carrier substrate, the first die package comprising a first die, forming a first redistribution layer over and coupled to the first die, the first redistribution layer including one or more metal layers disposed in one or more dielectric layers, adhering a second die over the redistribution layer, laminating a first dielectric material over the second die and the first redistribution layer, forming first vias through the first dielectric material to the second die and forming second vias through the first dielectric material to the first redistribution layer, and forming a second redistribution layer over the first dielectric material and over and coupled to the first vias and the second vias.

3D package structure and methods of forming same

A structure and a formation method of a semiconductor device are provided. The semiconductor device structure includes a semiconductor substrate and an interconnection structure over the semiconductor substrate. The semiconductor device structure also includes a first conductive pillar over the interconnection structure. The first conductive pillar has a first protruding portion extending towards the semiconductor substrate from a lower surface of the first conductive pillar. The semiconductor device structure further includes a second conductive pillar over the interconnection structure. The second conductive pillar has a second protruding portion extending towards the semiconductor substrate from a lower surface of the second conductive pillar. The first conductive pillar is closer to a center point of the semiconductor substrate than the second conductive pillar. A bottom of the second protruding portion is wider than a bottom of the first protruding portion.

Structure and formation method of semiconductor device with conductive bumps

An apparatus for forming a package structure is provided. The apparatus includes a processing chamber for bonding a first package component and a second package component. The apparatus also includes a bonding head disposed in the processing chamber. The bonding head includes a plurality of vacuum tubes communicating with a plurality of vacuum devices. The apparatus further includes a nozzle connected to the bonding head and configured to hold the second package component. The nozzle includes a plurality of first holes that overlap the vacuum tubes. The nozzle also includes a plurality of second holes offset from the first holes, wherein the second holes overlap at least two edges of the second package component. In addition, the apparatus includes a chuck table disposed in the processing chamber, and the chuck table is configured to hold and heat the first package component.

Apparatus and method for forming a package structure

A structure and a formation method of a semiconductor device are provided. The semiconductor device structure includes an interconnection structure over a semiconductor substrate. The semiconductor device structure includes a conductive pillar over the interconnection structure. The conductive pillar has a protruding portion extending towards the semiconductor substrate. The semiconductor device structure includes an upper conductive via between the conductive pillar and the interconnection structure. A center of the upper conductive via is laterally separated from a center of the protruding portion by a first distance. The semiconductor device structure includes a lower conductive via between the upper conductive via and the interconnection structure. The lower conductive via is electrically connected to the conductive pillar through the upper conductive via. A center of the lower conductive via is laterally separated from the center of the protruding portion by a second distance that is shorter than the first distance.

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Taoyuan, Taiwan

Hui-Min Huang