Intel Corporation

Hui-Min Chuang

Van H Le

Bernhard Sell

Travis W LaJoie

Allen B Gardiner

Shu Zhou

Yu-Wen Huang

Abhishek Anil Sharma

Xiaojun Weng

Cheng Tan

Techniques are provided herein for forming transistor devices with reduced parasitic capacitance, such as transistors used in a memory structure. In an example, a given memory structure includes memory cells, with a given memory cell having an access device and a storage device. The access device may include, for example, a thin film transistor (TFT), and the storage device may include a capacitor. Any of the given TFTs may include a dielectric liner extending along sidewalls of the TFT. The TFT includes a recess (e.g., a dimple) that extends laterally inwards toward a midpoint of a semiconductor region of the TFT. The dielectric liner thus also pinches or otherwise extends inward. This pinched-in dielectric liner may reduce parasitic capacitance between the contacts of the TFT and the gate electrode of the TFT. The pinched-in dielectric liner may also protect the contacts from forming too deep into the semiconductor region.

Dielectric sidewall features for tuning thin film transistor (TFT) parasitics

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Hillsboro, OR, United States of America

Hui-Min Chuang