United Microelectronics Corp.

Hui-Ling Huang

Benjamin Szu-Min Lin

Nien-Chung Li

George Liu

Vencent Chang

Ming-Shing Chen

Anseime Chen

Li-Shiun Chen

Cheng-Chung Chen

Hsin Tai

Andersen Chang

A method for manufacturing MOS transistor with hybrid hard mask includes providing a substrate having a dielectric layer and a polysilicon layer thereon, forming a hybrid hard mask having a middle hard mask and a spacer hard mask covering sidewalls of the middle hard mask on the polysilicon layer, performing a first etching process to etch the polysilicon layer and the dielectric layer through the hybrid hard mask to form a gate structure, performing a second etching process to form recesses in the substrate at two sides of the gate structure, and performing a SEG process to form epitaxial silicon layers in each recess.

Method for manufacturing MOS transistors utilizing a hybrid hard mask

There is a grain phenomenon issue of rough sidewall for patterning. Thus, imprecise grain profiles would be observed. As the critical dimensions of integrated circuit microelectronics fabrication device have decreased, the effect of grain phenomenon have become more pronounced. A profile improvement method with a thermal-compressive material and a thermal-compressive process is provided to solve the grain phenomenon issue for baseline of 0.09 um generation and beyond. With this material, the profile can be improved no matter in top view or lateral view. Furthermore, there are 0.1 um IDOF improvement and better physical etching performance.

Profile improvement method for patterning

A method for shrinking critical dimension of semiconductor devices includes forming a first pattern of a photoresist layer on a semiconductor device layer, by performing a blanket exposing process to expose the photoresist layer and the exposed semiconductor device layer to light having a wavelength that can be absorbed by the photoresist layer to provide the photoresist layer with a predetermined energy per unit area, thereby producing photo generated acids therein. A first thermal process is performed to diffuse the photo-generated acids formed within the photoresist layer and to equalize glass transition temperature (T ) of the photoresist layer. A second thermal process is thereafter carried out. The first thermal process is carried out under a temperature lower than T of the photoresist layer.

Method for shrinking critical dimension of semiconductor devices

The present invention is directed to a method for planarizing BARC layer in dual damascene process. For forming a dual damascene interconnect structure, by use of the present invention, a planar topography of the BARC layer is achieved by chemical mechanical polishing. The present invention applies a low temperature to bake the coated BARC layer before BARC material cross-links and induces the anti-reflective characteristic. Then, the BARC layer is planarized by chemical mechanical polishing. Next, a high temperature baking of the BARC layer is provided before coating the photoresist, so formation of the BARC layer is controlled with minimized variation in surface level and has the antireflective characteristic. Thus, the profile distortion on the via and the critical dimension control for the via are improved by patterning the via on a planar and an anti-reflective surface.

Method for planarizing barc layer in dual damascene process

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Tai-Chung, Taiwan

Hui-Ling Huang