Taiwan Semiconductor Manufacturing Comp. Ltd.

Hui-Lin Chang

Yung-Cheng Lu

Syun-Ming Jang Jang

Hung Chun Tsai

Chung-Chi Ko

Chen-Hua Douglas Yu

Ting-Yu Shen

Keng-Chu Lin

Chih-Hsien Lin

Lih-Ping Li

Pi-Tsung Chen

Tien I Bao

Yun-Chen Lu

Shau-Lin Shue

Tien-I Bao

Ming-Hsing Tsai

Hung-Wen Su

Ming-Shih Yeh

Chien-Hsueh Shih

Yung-Chen Lu

I-i Chen

Syun-Ming Jeng

An integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; a conductive wiring in the dielectric layer; and a metal carbide cap layer over the conductive wiring.

Carbonization of metal caps

A method of manufacturing a semiconductor device with a cap layer for a copper interconnect structure formed in a dielectric layer is provided. In an embodiment, a conductive material is embedded within a dielectric layer, the conductive material comprising a first material and having either a recess, a convex surface, or is planar. The conductive material is silicided to form an alloy layer. The alloy layer comprises the first material and a second material of germanium, arsenic, tungsten, or gallium.

Interconnect structure for semiconductor devices

A method of forming an integrated circuit includes providing a semiconductor substrate, forming a metallization layer over the semiconductor substrate, wherein the metallization layer comprises a metal feature in a low-k dielectric layer and extending from a top surface of the low-k dielectric layer into the low-k dielectric layer, performing a treatment to the low-k dielectric layer to form a hydrophilic top surface, and plating a cap layer on the metal feature in a solution.

Methods for improving uniformity of cap layers

A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, a conductive layer is located within a dielectric layer and a top surface of the conductive layer has either a recess, a convex surface, or is planar. An alloy layer overlies the conductive layer and is a silicide alloy having a first material from the conductive layer and a second material of germanium, arsenic, tungsten, or gallium.

A method of forming an integrated circuit structure, the method includes providing a semiconductor substrate; forming a dielectric layer over the semiconductor substrate; forming an opening in the dielectric layer; forming a seed layer in the opening; forming a copper line on the seed layer, wherein at least one of the seed layer and the copper line includes an alloying material; and forming an etch stop layer on the copper line.

Synergy effect of alloying materials in interconnect structures

A method of lowering the dielectric constant of an organosilicon low k dielectric layer while improving the hardness and thermal stability is provided. A deposited layer of carbon doped oxide, HSQ, or MSQ is cured and treated with a He plasma which improves hardness for a subsequent CMP step and lowers the dielectric constant. There is no loss of HO or CHduring the He treatment. The low k dielectric layer is then treated with a Hplasma which converts some of the Si&#x2014;O and Si&#x2014;CHbonds near the surface to Si&#x2014;H bonds, thereby further lowering the dielectric constant and increasing thermal stability that improves breakdown resistance. Moisture uptake is also reduced. The method is especially useful for interconnect schemes with deep sub-micron ground rules. Surprisingly, the k value obtained from two different plasma treatments is lower than when two He treatments or two Htreatment are performed.

Two step post-deposition treatment of ILD layer for a lower dielectric constant and improved mechanical properties

An interconnect structure of an integrated circuit and a method for forming the same are provided. The interconnect structure includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a conductor in the low-k dielectric layer, and a cap layer on the conductor. The cap layer has at least a top portion comprising a metal silicide/germanide.

Interconnect structure having a silicide/germanide cap layer

A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, the cap layer may be formed by an in-situ deposition process in which a process gas comprising germanium, arsenic, tungsten, or gallium is introduced, thereby forming a copper-metal cap layer. In another embodiment, a copper-metal silicide cap is provided. In this embodiment, silane is introduced before, during, or after a process gas is introduced, the process gas comprising germanium, arsenic, tungsten, or gallium. Thereafter, an optional etch stop layer may be formed, and a second dielectric layer may be formed over the etch stop layer or the first dielectric layer.

An interconnect structure with improved reliability is provided. The interconnect structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; a metallic wiring in the dielectric layer; a pre-layer over the metallic wiring, wherein the pre-layer contains boron; and a metal cap over the pre-layer, wherein the metal cap contains tungsten, and wherein the pre-layer and the metal cap are formed of different materials.

Selective formation of boron-containing metal cap pre-layer

A novel method for enhancing interface adhesion between adjacent dielectric layers, particularly between an etch stop layer and an overlying dielectric layer having a low dielectric constant (k) in the formation of metal interconnects during the fabrication of integrated circuits on semiconductor wafer substrates. The method may include providing a substrate, providing an etch stop layer on the substrate, providing an oxygen-rich dielectric pre-layer on the etch stop layer and providing a major dielectric layer on the oxygen-rich dielectric pre-layer. Metal interconnects are then formed in the dielectric layers. The oxygen-rich dielectric pre-layer between the etch stop layer and the upper dielectric layer prevents or minimizes peeling and cracking of the layers induced by stresses that are caused by chemical mechanical planarization of metal layers and/or chip packaging.

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Hsin-Chu, Taiwan

Hui-Lin Chang