Lam Research Corporation

Honeywell International Inc.

Alliedsignal Inc.

Novellus Systems Incorporated

Colgate Palmolive Company

Other

Hui-Jung Wu

James S Drage

Jengyi Yu

Richard Stephan Wise

Teresa A Ramos

Yang Pan

Boris Volosskiy

Douglas M Smith

Nagraj Shankar

Samantha S H Tan

Nader Shamma

Kaushik Chattopadhyay

Yu Jiang

Bart Jan Van Schravendijk

Roey Shaviv

Meihua Shen

Stephen C Wallace

John Hoang

Lisa Beth Brungardt

Neil Viernes

Sivananda K Kanakasabapathy

Mandyam Sriram

Girish Anant Dixit

Yongsik Yu

Richard A Spear

Teresa Baldwin

Mary Richey

Thorsten B Lill

Samantha SiamHwa Tan

Yigal Dov Blum

Kevin H Roderick

Pramod Subramonium

Paul Joseph Vincenti

Keith Fox

Michael S Mendolia

Tian-An Chen

Anna M George

Seongjun Heo

Tom Mountsier

Thomas Joseph Knisley

Prithu Sharma

Gengwei Jiang

Gereng Gunawan

Kreistler S Y Lau

Bhadri N Varadarajan

Hans-Werner Schmidt

George Andrew Antonelli

Denis H Endisch

Thomas W Mountsier

Mark Naoshi Kawaguchi

Daniel R Juliano

Roger Leung

Anthony J Esposito

Ananda K Banerji

Gowri Kamarthy

Morton L Barr

Jennifer O'Loughlin

Paul G Apen

Arpan Pravin Mahorowala

Kevin M McLaughlin

William T Lee

Jialing Yang

Nathan Musselwhite

Wenya Fan

Nicole Rutherford

Jay E Uglow

Wen Wu

Hao Chi

Elizabeth Apen

Kimberly Branshaw

Ron Katsanes

John Silkonia

Gisbert Riess

Huiyong Paul Chen

Huiyong (Paul) Chen

Aaron Lynn Routzahn

Nicholas Dominic Altieri

Kimberly Shafi

Jennifer O`Loughlin

A method of processing a substrate includes: providing a substrate having one or more mandrels comprising a mandrel material, wherein a layer of a spacer material coats horizontal surfaces and sidewalls of the one or more mandrels; and etching and completely removing the layer of the spacer material from the horizontal surfaces of the one or more mandrels and thereby exposing the mandrel material, without completely removing the spacer material residing at the sidewalls of the one or more mandrels. The etching includes exposing the substrate to a plasma formed using a mixture comprising a first gas and a polymer-forming gas, and wherein the etching comprises forming a polymer on the substrate. Polymer-forming gas may include carbon (C) and hydrogen (H).

Tin oxide films in semiconductor device manufacturing

Tin oxide film on a semiconductor substrate is etched selectively in a presence of photoresist by exposing the substrate to at least one of hydrogen-based chemistry and chlorine-based chemistry. In some implementations, a method of processing a semiconductor substrate starts by providing a semiconductor substrate having a patterned photoresist layer overlying a tin oxide layer. Next, openings are etched in the tin oxide layer using the patterned photoresist layer as a mask, and using at least one of a hydrogen-based etch chemistry and a chlorine-based etch chemistry. After the openings have been etched in the tin oxide layer, the photoresist layer is removed using an oxygen-based etch chemistry.

Tin oxide films are used as mandrels in semiconductor device manufacturing. In one implementation the process starts by patterning a tin oxide layer using at least one of a hydrogen-based etch chemistry and a chlorine-based etch chemistry, and using patterned photoresist as a mask, thereby providing a substrate having a plurality of protruding tin oxide features (mandrels). Next, a conformal layer of spacer material is formed both on the horizontal surfaces and on the sidewalls of the mandrels. The spacer material is then removed from the horizontal surfaces exposing the tin oxide material of the mandrels, without fully removing the spacer material residing at the sidewalls of the mandrels. Next, mandrels are selectively removed (e.g., using hydrogen-based etch chemistry), while leaving the spacer material that resided at the sidewalls of the mandrels. The resulting spacers can be used for patterning underlying layers on the substrate.

Tin oxide mandrels in patterning

Tin oxide film on a semiconductor substrate is etched selectively with an etch selectivity of at least 10 in a presence of silicon (Si), carbon (C), or a carbon-containing material (e.g., photoresist) by exposing the substrate to a process gas comprising hydrogen (H) and a hydrocarbon (e.g., at a hydrogen/hydrocarbon ratio of at least 5), such that a carbon-containing polymer is formed on the substrate. In some embodiments an apparatus for processing a semiconductor substrate includes a process chamber configured for housing the semiconductor substrate and a controller having program instructions on a non-transitory medium for causing selective etching of a tin oxide layer on a substrate in a presence of silicon, carbon, or a carbon-containing material by exposing the substrate to a plasma formed in a process gas that includes Hand a hydrocarbon.

Methods for forming patterned multi-layer stacks including a metal-containing layer are provided herein. Methods involve using silicon-containing non-metal materials in a multi-layer stack including one sacrificial layer to be later removed and replaced with metal while maintaining etch contrast to pattern the multi-layer stack and selectively remove the sacrificial layer prior to depositing metal. Methods involve using silicon oxycarbide in lieu of silicon nitride, and a sacrificial non-metal material in lieu of a metal-containing layer, to fabricate the multi-layer stack, pattern the multi-layer stack, selectively remove the sacrificial non-metal material to leave spaces in the stack, and deposit metal-containing material into the spaces. Sacrificial non-metal materials include silicon nitride and doped polysilicon, such as boron-doped silicon.

Film stack simplification for high aspect ratio patterning and vertical scaling

Methods and apparatuses for processing semiconductor substrates in an integration scheme to form chamferless vias are provided herein. Methods include bifurcating etching of dielectric by depositing a conformal removable sealant layer having properties for selective removal relative to dielectric material without damaging dielectric material. Some methods include forming an ashable conformal sealant layer. Methods also include forming hard masks including a Group IV metal and removing conformal removable sealant layers and hard masks in one operation using same etching chemistries.

Chamfer-less via integration scheme

A three-dimensional (3D) memory structure includes memory cells and a plurality of oxide layers and a plurality of word line layers. The plurality of oxide layers and the plurality of word line layers are alternately stacked in a first direction. A plurality of double channel holes extend through the plurality of oxide layers and the plurality of word line layers in the first direction. The plurality of double channel holes have a peanut-shaped cross-section in a second direction that is transverse to the first direction.

Self-aligned vertical integration of three-terminal memory devices

Tin oxide films are used as mandrels in semiconductor device manufacturing. In one implementation the process starts by providing a substrate having a plurality of protruding tin oxide features (mandrels) residing on an exposed etch stop layer. Next, a conformal layer of spacer material is formed both on the horizontal surfaces and on the sidewalls of the mandrels. The spacer material is then removed from the horizontal surfaces exposing the tin oxide material of the mandrels, without fully removing the spacer material residing at the sidewalls of the mandrel (e.g., leaving at least 50%, such as at least 90% of initial height at the sidewall). Next, mandrels are selectively removed (e.g., using hydrogen-based etch chemistry), while leaving the spacer material that resided at the sidewalls of the mandrels. The resulting spacers can be used for patterning the etch stop layer and underlying layers.

Tin oxide film on a semiconductor substrate is etched selectively in a presence of silicon (Si), carbon (C), or a carbon-containing material (e.g., photoresist) by exposing the substrate to a process gas comprising hydrogen (H) and a hydrocarbon. The hydrocarbon significantly improves the etch selectivity. In some embodiments an apparatus for processing a semiconductor substrate includes a process chamber configured for housing the semiconductor substrate and a controller having program instructions on a non-transitory medium for causing selective etching of a tin oxide layer on a substrate in a presence of silicon, carbon, or a carbon-containing material by exposing the substrate to a plasma formed in a process gas that includes Hand a hydrocarbon.

Tin oxide films are used as spacers and hardmasks in semiconductor device manufacturing. In one method, tin oxide layer is formed conformally over sidewalls and horizontal surfaces of protruding features on a substrate. A passivation layer is then formed over tin oxide on the sidewalls, and tin oxide is then removed from the horizontal surfaces of the protruding features without being removed at the sidewalls of the protruding features. The material of the protruding features is then removed while leaving the tin oxide that resided at the sidewalls of the protruding features, thereby forming tin oxide spacers. Hydrogen-based and chlorine-based dry etch chemistries are used to selectively etch tin oxide in a presence of a variety of materials. In another method a patterned tin oxide hardmask layer is formed on a substrate by forming a patterned layer over an unpatterned tin oxide and transferring the pattern to the tin oxide.

Methods and techniques for fabricating metal interconnects, lines, or vias by subtractive etching and liner deposition methods are provided. Methods involve depositing a blanket copper layer, removing regions of the blanket copper layer to form a pattern, treating the patterned metal, depositing a copper-dielectric interface material such that the copper-dielectric interface material adheres only to the patterned copper, depositing a dielectric barrier layer on the substrate, and depositing a dielectric bulk layer on the substrate.

Liner and barrier applications for subtractive metal integration

A dielectric diffusion barrier is deposited on a substrate that has a via and an overlying trench etched into an exposed layer of inter-layer dielectric, wherein there is exposed metal from the underlying interconnect at the bottom of the via. In order to provide a conductive path from the underlying metallization layer to the metallization layer that is being formed over it, the dielectric diffusion barrier is formed selectively on the inter-layer dielectric and not on the exposed metal at the bottom of the via. In one example a dielectric SiNC diffusion barrier layer is selectively deposited on the inter-layer dielectric using a remote plasma deposition and a precursor that contains both silicon and nitrogen atoms. Generally, a variety of dielectric diffusion barrier materials with dielectric constants of between about 3.0-20.0 can be selectively formed on inter-layer dielectric.

Selective formation of dielectric barriers for metal interconnects in semiconductor devices

Disclosed methods cap exposed surfaces of copper lines with a layer of metal or metal-containing compound combined with silicon. In some cases, the metal or metal-containing compound forms an atomic layer. In certain embodiments, the methods involve exposing the copper surface first to a metal containing precursor to form an atomic layer of adsorbed precursor or metal atoms, which may optionally be converted to an oxide, nitride, carbide, or the like by, e.g., a pinning treatment. Subsequent exposure to a silicon-containing precursor may proceed with or without metallic atoms being converted.

Metal and silicon containing capping layers for interconnects

Adhesive layers residing at an interface between metal lines and dielectric diffusion barrier (or etch stop) layers are used to improve electromigration performance of interconnects. Adhesion layers are formed by depositing a precursor layer of metal-containing material (e.g., material containing Al, Ti, Ca, Mg, etc.) over an exposed copper line, and converting the precursor layer to a passivated layer (e.g., nitridized layer). For example, a substrate containing exposed copper line having exposed Cu&#x2014;O bonds is contacted with trimethylaluminum to form a precursor layer having Al&#x2014;O bonds and Al&#x2014;C bonds on copper surface. The precursor layer is then treated to remove residual organic substituents and to form Al&#x2014;N, Al&#x2014;H bonds or both. The treatment can include direct plasma treatment, remote plasma treatment, UV-treatment, and thermal treatment with a gas such as NH, H, N, and mixtures thereof. A dielectric diffusion barrier layer is then deposited.

Interfacial capping layers for interconnects

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Fremont, CA, United States of America

Hui-Jung Wu