Taiwan Semiconductor Manufacturing Comp. Ltd.

Hui-Cheng Chang

Xiong-Fei Yu

Huan-Just Lin

Li-Ting Wang

De-Fang Chen

Teng-Chun Tsai

Cheng-Tung Lin

Syun-Ming Jang Jang

Ching-Feng Fu

Chun-Hung Lee

Liang-Yin Chen

Ming-Hsing Tsai

Huang-Yi Huang

Bing-Hung Chen

Chia-Yuan Chang

Chih-Hsin Ko

Chun-Hsiung Lin

Mao-Lin Huang

Chia-Cheng Chen

Chien-Hsun Wang

Chun-Heng Chen

Yu-Chan Yen

Meng-Shu Lin

Yee-Chia Yeo

Carlos H Diaz

Chia-Wei Hsu

Tsai-Yu Huang

Po-Kai Hsiao

Hong-Fa Luan

Pang-Yen Tsai

Wei-Jung Lin

Hung-Ta Lin

Hong-Mao Lee

Chi-Yuan Chen

Chia-Han Lai

Meng-Ku Chen

Wayne Liu

A semiconductor device includes first and second fins, first and second hafnium oxide layers, first and second cap layers, and first and second metal gate electrodes. The first and second fins protrude above a substrate and respectively have an n-channel region and a p-channel region. The first and second hafnium oxide layers wrap around the n-channel region and the p-channel region, respectively. The first and second cap layers wrap around the first and second annular hafnium oxide layers, respectively. The first and second cap layers are made of a same material that is lanthanum oxide, yttrium oxide, or strontium oxide. The first and second metal gate electrodes wrap around the first and second cap layers, respectively. The first and second metal gate electrodes have a same metal composition. The first and second gate dielectrics have a same dielectric composition.

Semiconductor device

A method for manufacturing a semiconductor device is provided. The method includes forming at least one epitaxial layer over a substrate; patterning the epitaxial layer into a semiconductor fin; depositing a conformal semiconductor capping layer over the semiconductor fin, wherein the conformal semiconductor capping layer has a first portion that is amorphous; performing a thermal treatment such that the first portion of the conformal semiconductor capping layer is converted from amorphous into crystalline; depositing a dielectric material over the conformal semiconductor capping layer; annealing the dielectric material, such that the conformal semiconductor capping layer is converted into a semiconductor-containing oxide layer; recessing the dielectric material and the semiconductor-containing oxide layer to form an isolation structure around the semiconductor fin; and forming a gate structure over the semiconductor fin and the isolation structure.

Method for manufacturing semiconductor device with semiconductor capping layer

A method for manufacturing a semiconductor device is provided. The method includes forming at least one epitaxial layer over a substrate; forming a mask over the epitaxial layer; patterning the epitaxial layer into a semiconductor fin; depositing a semiconductor capping layer over the semiconductor fin and the mask, wherein the semiconductor capping layer has a first portion that is amorphous on a sidewall of the mask; performing a thermal treatment such that the first portion of the semiconductor capping layer is converted from amorphous into crystalline; forming an isolation structure around the semiconductor fin; and forming a gate structure over the semiconductor fin.

Method for manufacturing semiconductor device

A semiconductor device includes first and second nanowire structures, first and second annular hafnium oxide layers, first and second annular cap layers, and first and second metal gate electrodes. The first and second nanowire structures are suspended over a substrate and respectively have an n-channel region and a p-channel region. The first and second annular hafnium oxide layers encircle the n-channel region and the p-channel region, respectively. The first and second annular cap layers encircle the first and second annular hafnium oxide layers, respectively. The first and second annular cap layers are made of a same material that is lanthanum oxide, yttrium oxide, or strontium oxide. The first and second metal gate electrodes encircle the first and second annular cap layers, respectively. The first and second metal gate electrodes have a same metal composition.

Devices are described herein that include an epitaxial layer, a cap layer above the epitaxial layer, a gate layer adjacent to the epitaxial layer on which an etching process is performed, a trench above the cap layer, and a source/drain portion includes the epitaxial layer.

Method of forming MOSFET structure

A semiconductor device includes a first vertical device having a first threshold and second vertical device having a second threshold. The first vertical device includes a first source; a first channel over the first source; a first drain over the first channel; a first conductive layer adjacent to the first channel; and a first gate adjacent to the first conductive layer. The second vertical device includes a second source; a second channel over the second source; a second drain over the second channel; a second conductive layer adjacent to the second channel; and a second gate adjacent to the second conductive layer.

Semiconductor device with multiple threshold voltage and method of fabricating the same

Disclosed is a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device includes forming a p-channel over a semiconductor substrate. A gate dielectric layer is formed over the p-channel. The gate dielectric layer is doped with a dopant. A first metal gate is formed over the gate dielectric layer.

Semiconductor devices and a method for forming the same are provided. In various embodiments, a method for forming a semiconductor device includes receiving a semiconductor substrate including a channel. An atmosphere-modulation layer is formed over the channel. An annealing process is performed to form an interfacial layer between the channel and the atmosphere-modulation layer.

Semiconductor device and method for forming the same

An embodiment fin field-effect-transistor (finFET) includes a semiconductor fin comprising a channel region and a gate oxide on a sidewall and a top surface of the channel region. The gate oxide includes a thinnest portion having a first thickness and a thickest portion having a second thickness different than the first thickness. A difference between the first thickness and the second thickness is less than a maximum thickness variation, and the maximum thickness variation is in accordance with an operating voltage of the finFET.

Fin field effect transistors having conformal oxide layers and methods of forming same

A semiconductor device includes an n-channel, a p-channel, a first gate dielectric layer, a second gate dielectric layer, a first metal gate electrode and a second metal gate electrode. The n-channel and the p-channel are made of different materials. The first gate dielectric layer is present on at least opposite sidewalls of the n-channel. The second gate dielectric layer is present on at least opposite sidewalls of the p-channel. The first metal gate electrode is present on the first gate dielectric layer. The second metal gate electrode is present on the second gate dielectric layer. The first metal gate electrode and the second metal gate electrode are made of substantially the same material.

Semiconductor device and method of manufacturing the same

A method includes providing a semiconductor structure that includes an epitaxial layer and a cap layer above the epitaxial layer, filling a trench above the cap layer with a sacrificial layer, and removing the sacrificial layer. As such, the cap layer is protected by the sacrificial layer during an etching process and the epitaxial layer is protected by the cap layer during another etching process.

A method of forming a channel of a gate structure is provided. A first epitaxial channel layer is formed within a first trench of the gate structure. A dry etching process is performed on the first epitaxial channel layer to form a second trench. A second epitaxial channel layer is formed within the second trench.

Gate structure

According to an exemplary embodiment, a chip is provided. The chip includes a first vertical device having a first threshold and second vertical device having a second threshold. The first vertical device includes a first source; a first channel over the first source; a first drain over the first channel; a first conductive layer adjacent to the first channel; and a first gate adjacent to the first conductive layer. The second vertical device includes a second source; a second channel over the second source; a second drain over the second channel; a second conductive layer adjacent to the second channel; and a second gate adjacent to the second conductive layer.

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Tainan, Taiwan

Hui-Cheng Chang