Trw Limited

Hugo W Chan

Arnold H Silver

Robert D Sandell

James M Murduck

Szutsun S Ou

Bruce J Dalrymple

Kenneth P Daly

Eugene L Dines

Susanne L Thomasson

A high temperature superconductor junction and a method of forming the junction are disclosed. The junction 40 comprises a first high-T.sub.c superconductive layer (first base electrode layer) 46 on a substrate 42 and a dielectric layer 48 on the first high-T.sub.c superconductive layer. The dielectric layer and the first high-T.sub.c superconductive layer define a ramp edge 50. A trilayer SNS structure 52 is disposed on the ramp edge to form an SSNS junction. The SNS structure comprises a second high-T.sub.c superconductive layer (second base electrode layer) 54 directly on the first high-T.sub.c superconductive layer, a normal barrier layer 56 on the second high-T.sub.c superconductive layer, and a third high-T.sub.c superconductive layer 58 (counterelectrode) on the barrier layer. The ramp edge is typically formed by photoresist masking and ion-milling. A plasma etch step can be performed in-situ to remove the photoresist layer 62 following formation of the ramp edge. A normal-superconductive (NS) structure can be optimally formed directly on the ramp edge following the plasma etch step to form an SNS junction 70. The SNS and NS structures are preferably formed in-situ.

Method of making high-T.sub.c SSNS and SNS Josephson junction

A method of fabricating a low-inductance, in-line resistor includes the steps of: depositing a superconductive layer 12 on a base layer 14; patterning an interconnect region 16 on the superconductive layer 12; and converting the interconnect region 16 of the superconductive layer 12 to a resistor material region 18. The resistor region 18 and the superconductive layer 12 are substantially in the same plane. The method can further include the steps of depositing a conductive layer 22 on the resistor region 18 and on the photo-resist layer 20, and lifting off the photo-resist layer 20 to leave the conductive layer 22 on the resistor region 18. As such, the conductive layer 22 provides a low sheet resistivity for the resistor region 18. In another embodiment, the method includes the steps of: depositing in-situ a superconductive layer 12 on a base layer 14; depositing in-situ a conductive layer 22 on the superconductive layer 12 to form a bi-layer 24; patterning an interconnect region 16 on the bi-layer 24; and converting the interconnect region 16 of the bi-layer 24 to a resistor material region 18.

Method of fabricating a low-inductance in-line resistor for

Planar in-line resistors for superconductor circuits

A high temperature superconductor junction and a method of forming the junction are disclosed. The junction 40 comprises a first high-T.sub.c, superconductive layer (first base electrode layer) 46 on a substrate 42 and a dielectric layer 48 on the first high-T.sub.c, superconductive layer. The dielectric layer and the first high-T.sub.c superconductive layer define a ramp edge 50. A trilayer SNS structure 52 is disposed on the ramp edge to form an SSNS junction. The SNS structure comprises a second high-T.sub.c, superconductive layer (second base electrode layer) 54 directly on the first high-T.sub.c superconductive layer, a normal barrier layer 56 on the second high-T.sub.c superconductive layer, and a third high-T.sub.c superconductive layer 58 (counterelectrode) on the barrier layer. The ramp edge is typically formed by photoresist masking and ionmilling. A plasma etch step can be performed in-situ to remove the photoresist layer 62 following formation of the ramp edge. A normal-superconductive (NS) structure can be optimally formed directly on the ramp edge following the plasma etch step to form an SNS junction 70. The SNS and NS structures are preferably formed in-situ.

High-temperature SSNS and SNS Josephson junction and method of making

A multi-state Josephson memory in a superconductor integrated circuit includes a plurality of superconductive quantum interference device (SQUID) memory cells 2 each having a SQUID 4 characterized by a SQUID loop inductance L and a junction critical current I.sub.c, which determine the number of memory states that can be stored in the SQUID 4. A gate current I.sub.g is transmitted to the superconductive inductors 6 and 8 of the SQUID 4 to perform a read operation by crossing a designated number of current threshold boundaries corresponding to the memory state stored in the SQUID, so that the Josephson junction 12 of the SQUID 4 generates a number of pulses corresponding to the memory state. A control current I.sub.con writes data to the SQUID 4 through a control current input 16, and is preferably magnetically coupled to the SQUID 4 through superconductive inductor pairs 18, 6 and 20, 8. In a preferred embodiment, a plurality of SQUID memory cells 70a, 70b, . . . 70f are arranged in a plurality of columns and rows with column select inputs 72, 74 and row select inputs 76, 78 and 80. Digital-to-analog converters 86 and 88 are preferably provided to convert a binary digital input into the analog control current I.sub.con, the magnitude of which is designed to cross a number of current threshold boundaries corresponding to the digital input. A plurality of single flux quantum counters 112 and 114 are preferably connected to count the number of Josephson pulses from the SQUID memory cells 70a, 70b, . . . 70f to generate a count of the pulses as the memory output. In a preferred embodiment, the memory outputs from the single flux quantum counters 112 and 114 are fed back into the input digital-to-analog converters 86 and 88, respectively, to form a non-destructive readout.

Multi-state Josephson memory

A SQUID 10 was multiple junctions, each junction allowing a critical current to flow therethrough. The SQUID 10 comprises a laminar structure including: (a) a substantially planar substrate 12; (b) a first high temperature superconductive layer 14 of substantially uniform thickness deposited on the substrates; (c) a dielectric layer 16 deposited on the first superconductive layer 14, the dielectric layer 16 comprising a planar level segment 18 having two ramp segments defining SQUID junctions at opposing ends 20 and defining SQUID hole; and (d) a second high temperature superconductive layer 24 of substantially uniform thickness deposited on the dielectric layer 16, the second high temperature superconductive layer 24 covering all three segments of the dielectric layer 16. A magnetic field substantially parallel to the substrate applied to the SQUID hole modulates a critical current flowing through the junctions while minimizing magnetic field penetration into the junctions and minimizing SQUID loop inductance.

Superconductive quantum interference device for digital logic circuits

A superconductive electrical device is operable simultaneously at relatively higher temperatures, i.e., 60-90K, and at relatively lower temperatures, i.e., less than 12K. The device comprises a non-superconductive substrate with two regions, a first relatively high temperature region and a second relatively low temperature region. A high temperature superconductor is on the first region and a portion of the second region. A dielectric layer is on the high temperature superconductor. A low temperature superconductor is on the second region of the substrate and on a portion of the dielectric layer. Integrated circuit chips can be secured to both superconductors, thereby yielding a superconductive multi-chip module operable at two different temperatures, such as in a cryo-cooler with two temperature stages.

Method of forming a high performance low thermal loss bi-temperature

High performance, low thermal loss, bi-temperature superconductive device

A multi-layer superconductive interconnect structure includes a first multi-layer substrate with a first superconducting layer (SL) deposited on a first epitaxial substrate and a first glue dielectric layer (GDL) on the first SL. A second multi-layer substrate includes a second SL deposited on a second epitaxial substrate and a second GDL on said second SL. The first GDL and the second GDL are clamped and cured together to form a composite substrate.

Multi-layered superconductive interconnects

A high-speed gamma pulse suppression circuit employing a frequency discrimination and sampling technique for elimination of gamma induced noise from semiconductor infrared detectors. The gamma pulse suppression circuit includes a high pass filter for separating high-frequency gamma induced pulses from a detector signal and a gamma pulse detector for detecting the gamma induced pulses. The gamma pulse suppression circuit is connected in parallel with a detector readout circuit such that the suppression circuit causes the readout circuit to discard samples of the detector signal in which gamma induced pulses are detected. The gamma pulse suppression circuit provides effective and efficient real time gamma pulse suppression by completely eliminating the detected gamma pulses from the detector signal, while preserving the quality of the signal.

High-speed gamma pulse suppression circuit for semiconductor infrared

A monolithically-integrated semiconductor/ superconductor infrared detector and readout circuit providing sensitive, low-noise detection of infrared radiation for high-performance focal plane array applications. The infrared detector and readout circuit includes a semiconductor infrared detector and a semiconductor/superconductor transimpedance readout amplifier fabricated directly on the infrared detector using thin-film, integrated-circuit processing techniques. A superconducting analog-to-digital (A/D) converter digitizes the detector signals in the cryogenically cooled environment of the detector before coupling the signals to the much warmer and electromagnetically noisier environment of the back-end signal processing electronics, thus reducing noise contamination.

Monolithically-integrated semiconductor/superconductor infrared detector

A Josephson junction and a method for its fabrication in which a laminated junction layer is formed in situ on the side edge of a base electrode contact. The laminated junction layer forms the Josephson junction of the present invention and includes an insulating or barrier layer sandwiched between a superconducting base electrode and a superconducting counter electrode. The Josephson junction is formed on the side edge of the base electrode contact to allow very small junction areas to be fabricated using conventional optical lithographic techniques, such as photolithography. The laminated junction layer is formed in situ, with the three layers of the laminated junction layer being formed successively without removing the device from the controlled atmosphere of the deposition system, to prevent contamination of the junction region.

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Rancho Palos Verdes, CA, United States of America

Hugo W Chan