Taiwan Semiconductor Manufacturing Comp. Ltd.

Huang-Lin Chao

Chung-Liang Cheng

Ziwei Fang

Chen-Hao Wu

Hsiang-Pi Chang

Yao-Sheng Huang

Pinyen Lin

Teng-Chun Tsai

Lin-Yu Huang

Li-Zhen Yu

Yu-Yun Peng

Jung-Hung Chang

Shen-Nan Lee

Tzer-Min Shen

Chansyun David Yang

Hsu-Kai Chang

I-Ming Chang

Chun-Hung Liao

Chun-I Wu

Yen-Tien Tung

Han-De Chen

An-Hsuan Lee

Kenichi Sano

Kuei-Lin Chan

Yu-Chia Liang

Kuo-Liang Sung

Wei-Ting Yeh

Yi-Rui Chen

Zheng-Yong Liang

Shen-Yang Lee

Chia-Yun Cheng

A method for manufacturing a semiconductor structure includes: forming a first bonding layer on a device substrate, the first bonding layer including a first bonding sub-layer and a second bonding sub-layer, the first bonding sub-layer including a first metal oxide material in an amorphous state and a plurality of metal nanoparticles, the second bonding sub-layer including a second metal oxide material in an amorphous state; forming a second bonding layer on a carrier substrate, the second bonding layer including a third metal oxide material in an amorphous state; conducting a surface modification process on the first and second bonding layers; bonding the device and carrier substrates to each other through the first and second bonding layers; and annealing the first and second bonding layers to convert the first, second, and third metal oxide materials from the amorphous state to a crystalline state.

Metal nanoparticles in an amorphous bonding layer between a device substrate and carrier substrate

A semiconductor structure includes an interfacial layer disposed over a semiconductor channel region, a metal oxide layer disposed over the interfacial layer, a high-k gate dielectric layer disposed over the metal oxide layer, a metal halide layer disposed over the high-k gate dielectric layer, and a metal gate electrode disposed over the high-k gate dielectric layer. The metal oxide layer and the interfacial layer form a dipole moment. The metal oxide layer includes a first metal. The metal halide layer includes a second metal different from the first metal.

Tuning threshold voltage in field-effect transistors

A semiconductor device includes a channel layer, an interfacial layer, a gate dielectric layer, a gate electrode, dipole elements, and additional elements. The interfacial layer is disposed on the channel layer, and includes an insulating material. The gate dielectric layer is disposed over the interfacial layer such that the channel layer is separated from the gate dielectric layer by the interfacial layer. The gate electrode is disposed on the gate dielectric layer. The dipole elements are present in at least one of the interfacial layer and the gate dielectric layer in a predetermined amount such that the semiconductor device has a predetermined threshold voltage. The additional elements are located at a region where the dipole elements are present so as to reduce interfacial defects caused by the dipole elements. The additional elements are different from the dipole elements. Methods for manufacturing the semiconductor device are also disclosed.

Semiconductor device with tunable threshold voltage and method for manufacturing the same

A method is provided for forming a contact plug by bottom-up metal growth. In one step, a substrate is etched to form a contact hole that exposes a silicon-containing feature in the substrate. In one step, a silicide layer is formed on the silicon-containing feature. In one step, a metal seed layer is formed over the silicide layer. In one step, a metal contact layer is deposited over the metal seed layer to form the contact plug in the contact hole.

Method for forming a contact plug by bottom-up metal growth

A semiconductor device structure is provided. The semiconductor device structure includes a source/drain epitaxial feature disposed over a substrate, a plurality of semiconductor layers disposed parallelly to each other and in contact with the source/drain epitaxial feature, a gate electrode layer surrounding a portion of each of the plurality of semiconductor layers, and a dielectric region in the substrate below the source/drain epitaxial feature. The dielectric region includes a first oxidation region having a first dopant, and a second oxidation region having a second dopant different than the first dopant.

Semiconductor device structure including dielectric region with plurality of different oxidation regions

The method includes receiving a semiconductor device having a first surface and a second surface. The first surface is a top surface including a conductive material exposed thereon; and the second surface is an embedded surface including the conductive material and a dielectric material. The method also includes selecting a first polishing slurry to achieve a first polishing rate of the conductive material in the first polishing slurry and a second polishing rate of the dielectric material in the first polishing slurry. The method further includes selecting a second polishing slurry to achieve a third polishing rate of the conductive material in the second polishing slurry and a fourth polishing rate of the dielectric material in the second polishing slurry. The method additionally includes polishing the first surface with the first polishing slurry until the second surface is exposed; and polishing the second surface with the second polishing slurry.

Slurry compositions for chemical mechanical planarization

The embodiments described herein are directed to a method for the fabrication of transistors with aluminum-free n-type work function layers as opposed to aluminum-based n-type work function layers. The method includes forming a channel portion disposed between spaced apart source/drain epitaxial layers and forming a gate stack on the channel portion, where forming the gate stack includes depositing a high-k dielectric layer on the channel portion and depositing a p-type work function layer on the dielectric layer. After depositing the p-type work function layer, forming without a vacuum break, an aluminum-free n-type work function layer on the p-type work function layer and depositing a metal on the aluminum-free n-type work function layer. The method further includes depositing an insulating layer to surround the spaced apart source/drain epitaxial layers and the gate stack.

Work function layers for transistor gate electrodes

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Hsinchu, Taiwan

Huang-Lin Chao