Taiwan Semiconductor Manufacturing Comp. Ltd.

Huan-Just Lin

De-Fang Chen

Ching-Feng Fu

Chun-Hung Lee

Cheng-Tung Lin

Teng-Chun Tsai

Li-Ting Wang

Sheng-Liang Pan

Hun-Jan Tao

Yu-Lien Huang

Te-Chih Hsiung

Jyun-De Wu

Chih-Tang Peng

Yuan-Tien Tu

Peng Wang

Yu-Chan Yen

Chia-Ying Lee

Hui-Cheng Chang

Harry-Hak-Lay Chuang

Chia-Yang Hung

Bao-Ru Young

Ming-Ching Chang

Shao-Jyun Wu

Yung-Cheng Lu

Chien-Hsun Wang

Bing-Hung Chen

Tze-Liang Lee

Chien-Hao Chen

Pei-Ren Jeng

Jin-Aun Ng

Jen-Sheng Yang

Guan-Ren Wang

Ta-Wei Lin

Yi-Chen Wang

Chih-Yang Yeh

Jung-Hui Kao

Huang-Ming Chen

Hui-Wen Lin

Shih-Hao Lo

Shih-Chang Chen

Ming-Hsing Tsai

Huang-Yi Huang

Tsai-Jung Ho

Jiann-Horng Lin

Yi-Chun Chang

Chih-Hsin Ko

Tai-Chun Huang

Hsien-Ming Lee

Chia-Ching Lee

Shen-Nan Lee

Hung-Chin Chung

Bor-Wen Chan

Peng-Fu Hsu

Fang-Cheng Chen

Sin-Yi Yang

Han-Ting Lin

Chung-Chieh Lee

Bor Chiuan Hsieh

Chen-Jung Wang

Chia-Shiung Tsai

Jen-Cheng Liu

Wei Cheng Wu

Li-Te S Lin

Chi-Cheng Hung

Chien-An Chen

Sheng-Chen Chung

Yuan-Hung Chiu

Yi-Shien Mor

Ming-Jie Huang

Meng-Chun Chang

Yu-Jen Cheng

Yu-Feng Yin

Hak-Lay Chuang

Ru-Gun Liu

Chih-Ming Lai

Chao-Cheng Chen

Mong-Song Liang

Tsai-Sheng Gau

Ming-Hsi Yeh

Chun-Hsiung Lin

Chun-Kuang Chen

Yung-Sung Yen

Liang-Gi Yao

Shiang-Bau Wang

Wei-Liang Lin

Jr-Jung Lin

Hung-Chang Hsieh

Ming-Huan Tsai

Kuei Shun Chen

Chu-Yun Fu

Chia-Chu Liu

Hui-Chi Huang

Min-Hsiung Chiang

Mu-Chi Chiang

Chin-Yuan Tseng

An-Shen Chang

Li-Chih Chao

Chi-Kang Liu

Wen-Kuo Hsieh

Hsiao-Tzu Lu

A device includes source/drain epitaxial structures over a substrate, source/drain contacts over the source/drain epitaxial structures, respectively, a gate structure laterally between the source/drain contacts, a gate dielectric cap over the gate structure, an oxide-based etch-resistant layer over the gate dielectric cap, a nitride-based etch stop layer over the oxide-based etch-resistant layer, and an interlayer dielectric (ILD) layer over the nitride-based etch stop layer. The device further includes a via structure extending through the ILD layer, the nitride-based etch stop layer, and the oxide-based etch-resistant layer to electrically connect with the one of the source/drain contacts.

Etch profile control of via opening

A method for making a semiconductor device includes patterning at least one dielectric layer disposed over a conductive cap layer to form a via opening penetrating through the at least one dielectric layer to expose the conductive cap layer and to form a top portion of the conductive cap layer into a metal oxide layer; converting the metal oxide layer to a metal oxynitride layer by a soft ashing process using a processing gas containing nitrogen gas; removing the metal oxynitride layer from a remaining portion of the conductive cap layer; and forming a via contact in the via opening to electrically connect the remaining portion of the conductive cap layer.

Soft ashing process for forming protective layer on conductive cap layer of semiconductor device

A method of forming a semiconductor device includes: forming a metal gate structure over a fin that protrudes above a substrate, the metal gate structure being surrounded by an interlayer dielectric (ILD) layer; recessing the metal gate structure below an upper surface of the ILD layer distal from the substrate; after the recessing, forming a first dielectric layer over the recessed metal gate structure; forming an etch stop layer (ESL) over the first dielectric layer and the ILD layer; forming a second dielectric layer over the ESL; performing a first dry etch process to form an opening that extends through the second dielectric layer, through the ESL, and into the first dielectric layer; after the first dry etch process, performing a wet etch process to clean the opening; and after the wet etch process, performing a second dry etch process to extend the opening through the first dielectric layer.

Fin field-effect transistor device and method

According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.

Vertical device having a protrusion source

A method may include forming a mask layer on top of a first dielectric layer formed on a first source/drain and a second source/drain, and creating an opening in the mask layer and the first dielectric layer that exposes portions of the first source/drain and the second source/drain. The method may include filling the opening with a metal layer that covers the exposed portions of the first source/drain and the second source/drain, and forming a gap in the metal layer to create a first metal contact and a second metal contact. The first metal contact may electrically couple to the first source/drain and the second metal contact may electrically couple to the second source/drain. The gap may separate the first metal contact from the second metal contact by less than nineteen nanometers.

Gap patterning for metal-to-source/drain plugs in a semiconductor device

A method of forming a semiconductor device includes: forming a first conductive feature in a first dielectric layer disposed over a substrate; forming a second dielectric layer over the first dielectric layer; etching the second dielectric layer using a patterned mask layer to form an opening in the second dielectric layer, where the opening exposes the first conductive feature; performing an ashing process to remove the patterned mask layer after the etching; wet cleaning the opening after the ashing process, where the wet cleaning enlarges a bottom portion of the opening; and filling the opening with a first electrically conductive material.

Interconnect structure for semiconductor devices

A method for manufacturing a semiconductor device includes forming a first dielectric layer over a semiconductor fin. The method includes forming a second dielectric layer over the first dielectric layer. The method includes exposing a portion of the first dielectric layer. The method includes oxidizing a surface of the second dielectric layer while limiting oxidation on the exposed portion of the first dielectric layer.

Fin field-effect transistor and method of forming the same

In some embodiments, the present disclosure relates to an integrated circuit device. A transistor structure is disposed over a substrate and includes a pair of source/drain regions and a gate electrode between the pair of source/drain regions. A lower inter-layer dielectric (ILD) layer is disposed over the pair of source/drain regions and surrounds the gate electrode. The gate electrode is recessed from top of the lower ILD layer. A gate capping layer is disposed on the gate electrode. The gate capping layer has a top surface aligned or coplanar with that of the lower ILD layer.

Middle-of-line interconnect structure and manufacturing method

An improved work function layer and a method of forming the same are disclosed. In an embodiment, the method includes forming a semiconductor fin extending from a substrate; depositing a dielectric layer over the semiconductor fin; depositing a first work function layer over the dielectric layer; and exposing the first work function layer to a metastable plasma of a first reaction gas, a metastable plasma of a generation gas, and a metastable plasma of a second reaction gas, the first reaction gas being different from the second reaction gas.

Semiconductor device and method

A magnetic tunnel junction (MTJ) memory cell comprising a connection via structure, a bottom electrode disposed on the connection via structure, a memory material stack disposed on the bottom electrode, and a conductive contact structure disposed on the memory material stack, in which a bottom surface of the conductive contact structure is in direct contact with a memory material layer of the memory material stack.

Memory cell with low resistance top electrode contact and methods for forming the same

A semiconductor device includes a channel structure, a first gate structure straddling the channel structure, and an epitaxial structure. The epitaxial structure is adjacent to the first gate structure and is coupled to an end of the channel structure. The semiconductor device further includes a first contact structure disposed over and in contact with the epitaxial structure and a nitride-based conformal layer extending at least over the first contact structure. The semiconductor device further includes an oxide-based layer disposed over the nitride-based conformal layer. A portion of the nitride-based conformal layer, disposed over the first contact structure, has a dip that is filled with a first portion of the oxide-based layer.

Dielectric cap structure in semiconductor devices and methods of manufacturing the same

Semiconductor devices and methods of manufacturing the semiconductor devices are described herein. A method includes forming a first opening through a dielectric layer, the first opening exposing a conductive region. A wet cleaning is used after the forming the first opening, and the first opening is treated after the wet cleaning the first opening, the treating the first opening comprising turning a sidewall treatment precursor and a bottom treatment precursor into a first plasma mixture, the sidewall treatment precursor being different from the bottom treatment precursor. The first opening is filled with a conductive material after the treating the first opening.

Semiconductor devices and methods of manufacture

A method includes forming a first high-k dielectric layer over a first semiconductor region, forming a second high-k dielectric layer over a second semiconductor region, forming a first metal layer comprising a first portion over the first high-k dielectric layer and a second portion over the second high-k dielectric layer, forming an etching mask over the second portion of the first metal layer, and etching the first portion of the first metal layer. The etching mask protects the second portion of the first metal layer. The etching mask is ashed using meta stable plasma. A second metal layer is then formed over the first high-k dielectric layer.

Tuning threshold voltage through meta stable plasma treatment

Growing community of inventors

Hsinchu, Taiwan

Huan-Just Lin