Taiwan Semiconductor Manufacturing Comp. Ltd.

Huai-Tei Yang

Shih-Chieh Chang

Chun-Chieh Wang

Shahaji B More

Cheng-Han Lee

Kei-Wei Chen

Yueh-Ching Pai

Ziwei Fang

Chun-Hsiung Tsai

Kuo-Feng Yu

Chien-Tai Chan

Zheng-Yang Pan

Lun-Kuang Tan

Yu-Ting Lin

Huicheng Chang

Liang-Yin Chen

Su-Hao Liu

Chia-Cheng Chen

Kuo-Ju Chen

Chun-Hung Wu

Wei-Ming You

Shu Kuan

Chun Hsiung Tsai

Yi-Min Huang

Hsien-Ming Lee

Chang-Miao Liu

Yi-Jen Lai

Po-Yu Lin

Yi-Ting Wang

Tsung-Ta Tang

Chi-Yu Chou

Ming-Fa Wu

Chi-Jen Yang

Ying-Lang Wang

Chien-Chung Chen

Po-Chung Cheng

You-Hua Chou

Tzung-Chi Fu

Yun-Yue Lin

Chih-Teng Liao

Yu-Sheng Wang

Hon-Lin Huang

Yu-Chi Lin

Su-Yu Yeh

Kuo-Hsiu Wei

Wei-Jen Lo

Chien-Shun Liao

Chih-Kang Han

Chun-I Wu

Tang-Kuei Chang

Chien-Pin Chan

Chun Chieh Wang

Ying-Min Chou

Wen-Lung Ho

Chih-Yuan Chien

Yi-Ming Huang

En-Ting Lee

Kun-El Chen

Kuo-Jung Huang

Po Hsuan Li

Shiu-Ko JangJian

Hsi-Kuei Cheng

Yu-Ku Lin

Chun-Chang Chen

Chun Che Lin

Shih-Ho Lin

Chun-Che Lin

Wen-Chu Hsiao

Yu-Chen Wei

Chih-Yuan Yang

Jen-Chieh Lai

Kun-Ei Chen

Hsiu-Ting Chen

Chun-Yuan Hsu

Chin-Te Huang

Ching-Ling Lee

Jeng-Yang Pan

Kuo-Hung Liao

Szu-Cheng Wang

Jun-Yang Lai

Chun-Ju Huang

Yi-Lang Wang

Li-Hsiang Chao

Chia-Chun Wu

Wang Chun-Chieh

Cheng-Yang Pan

Ting-Chu Wang

Wen-Fang Tang

Suan-Jun Kuan

Chang-Maio Liu

A semiconductor device including a cap layer and a method for forming the same are disclosed. In an embodiment, a method includes epitaxially growing a first semiconductor layer over an N-well; etching the first semiconductor layer to form a first recess; epitaxially growing a second semiconductor layer filling the first recess; etching the second semiconductor layer, the first semiconductor layer, and the N-well to form a first fin; forming a shallow trench isolation region adjacent the first fin; and forming a cap layer over the first fin, the cap layer contacting the second semiconductor layer, forming the cap layer including performing a pre-clean process to remove a native oxide from exposed surfaces of the second semiconductor layer; performing a sublimation process to produce a first precursor; and performing a deposition process wherein material from the first precursor is deposited on the second semiconductor layer to form the cap layer.

Semiconductor device and method

A method of forming an integrated circuit structure includes forming a gate dielectric on a wafer, forming a work function layer over the gate dielectric, depositing a capping layer over the work function layer, soaking the capping layer in a silicon-containing gas to form a silicon-containing layer, forming a blocking layer after the silicon-containing layer is formed, and forming a metal-filling region over the blocking layer.

Silicon intermixing layer for blocking diffusion

Methods and devices are provided wherein rotational gas-flow is generated by vortex generators to decontaminate dirty gas (e.g., gas contaminated by solid particles) in pumping lines of vacuum systems suitable for use at a semiconductor integrated circuit fabrication facility. The vacuum systems use filterless particle decontamination units wherein rotational gas-flow is applied to separate and trap solid particles from gas prior to the gas-flow entering a vacuum pump. Methods are also described whereby solid deposits along portions of pumping lines may be dislodged and removed and portions of pumping lines may be self-cleaning.

Vacuum systems in semiconductor fabrication facilities

The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.

Formation and in-situ etching processes for metal layers

A method for cleaning debris and contamination from an etching apparatus is provided. The etching apparatus includes a process chamber, a source of radio frequency power, an electrostatic chuck within the process chamber, a chuck electrode, and a source of DC power connected to the chuck electrode. The method of cleaning includes placing a substrate on a surface of the electrostatic chuck, applying a plasma to the substrate, thereby creating a positively charged surface on the surface of the substrate, applying a negative voltage or a radio frequency pulse to the electrode chuck, thereby making debris particles and/or contaminants from the surface of the electrostatic chuck negatively charged and causing them to attach to the positively charged surface of the substrate, and removing the substrate from the etching apparatus thereby removing the debris particles and/or contaminants from the etching apparatus.

Etching apparatus and methods of cleaning thereof

The present disclosure describes an exemplary fin structure formed on a substrate. The disclosed fin structure comprises an n-type doped region formed on a top portion of the substrate, a silicon epitaxial layer on the n-type doped region, and an epitaxial stack on the silicon epitaxial layer, wherein the epitaxial stack comprises a silicon-based seed layer in physical contact with the silicon epitaxial layer. The fin structure can further comprise a liner surrounding the n-type doped region, and a dielectric surrounding the liner.

Fully strained channel

The present disclosure describes a method to form silicon germanium (SiGe) source/drain epitaxial stacks with a boron doping profile and a germanium concentration that can induce external stress to a fully strained SiGe channel. The method includes forming one or more gate structures over a fin, where the fin includes a fin height, a first sidewall, and a second sidewall opposite to the first sidewall. The method also includes forming a first spacer on the first sidewall of the fin and a second spacer on the second sidewall of the fin; etching the fin to reduce the fin height between the one or more gate structures; and etching the first spacer and the second spacer between the one or more gate structures so that the etched first spacer is shorter than the etched second spacer and the first and second etched spacers are shorter than the etched fin. The method further includes forming an epitaxial stack on the etched fin between the one or more gate structures.

Method of forming source/drain epitaxial stacks

In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.

P-type strained channel in a fin field effect transistor (FinFET) device

The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.

Doping for semiconductor device with conductive feature

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure, and a source/drain (S/D) epitaxial layer formed in the fin structure and adjacent to the gate structure. The semiconductor structure also includes a S/D silicide layer formed on the S/D epitaxial layer, and the S/D silicide layer has a first width, the S/D epitaxial layer has a second width, and the first width is smaller than the second width. The semiconductor structure includes a dielectric spacer between the gate structure and the S/D silicide layer, and a top surface of the dielectric spacer is lower than a top surface of the gate structure.

Semiconductor structure with source/drain multi-layer structure and method for forming the same

Semiconductor structures and method for forming the same are provide. The semiconductor structure includes a fin structure protruding from a substrate and a gate structure formed across the fin structure. The semiconductor structure further includes an Arsenic-doped region formed in the fin structure and a source/drain structure formed over the Arsenic-doped region. In addition, a bottommost portion of the Arsenic-doped region is lower than a bottommost portion of the source/drain structure.

Semiconductor structure with source/drain structure having modified shape

A finFET device and methods of forming are provided. The method includes etching recesses in a substrate on opposite sides of a gate stack. The method also includes epitaxially growing a source/drain region in each recess, where each of the source/drain regions includes a capping layer along a top surface of the respective source/drain region, and where a concentration of a first material in each source/drain region is highest at an interface of the capping layer and an underlying epitaxy layer. The method also includes depositing a plurality of metal layers overlying and contacting each of the source/drain regions. The method also includes performing an anneal, where after the anneal a metal silicide region is formed in each of the source/drain regions, where each metal silicide region extends through the capping layer and terminates at the interface of the capping layer and the underlying epitaxy layer.

FinFET device and method of forming

A method of using a polishing system includes securing a wafer in a carrier head, the carrier head including a housing enclosing the wafer, in which the housing includes a retainer ring recess and a retainer ring positioned in the retainer ring recess, the retainer ring surrounding the wafer, in which the retainer ring includes a main body portion and a bottom portion connected to the main body portion, and a bottom surface of the bottom portion includes at least one first engraved region and a first non-engraved region adjacent to the first engraved region; pressing the wafer against a polishing pad; and moving the carrier head or the polishing pad relative to the other.

Method and system for performing chemical mechanical polishing

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Hsinchu, Taiwan

Huai-Tei Yang