International Business Machines Corporation

Adeia Semiconductor Bonding Technologies Inc.

Adeia Semiconductor Solutions LLC

Huai Huang

Lawrence Alfred Clevenger

Christopher J Penny

Benjamin David Briggs

Michael Rizzolo

Hosadurga K Shobha

Bartlet H Deprospo

Nicholas Anthony Lanzillo

Ruilong Xie

Su Chen Fan

Chih-Chao Yang

Koichi Motoyama

Junli Wang

Heng Wu

Wei Wang

Robert Russell Robison

Dexin Kong

Robin Hsin Kuo Chao

Chanro Park

Son Van Nguyen

Alfred Grill

Takeshi Nogami

Christian Lavoie

Christopher Joseph Waskiewicz

James John Kelly

Dimitri Houssameddine

Prasad Bhosale

Tianji Zhou

Devika Sil

Benjamin D Briggs

Mary Breton

Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a first power plane electrically connected to a first plurality of via-to-backside power planes (VBPPs), a second power plane, and a plurality of pass through vias electrically connecting the second power plane to a second plurality of VBPPs, wherein the plurality of pass through vias pass through the first power plane.

Backside power plane

A semiconductor interconnect structure comprises a substrate, a plurality of metal lines disposed relative to the substrate and a plurality of first and second caps disposed on the metal lines wherein the first caps comprise a first dielectric material and the second caps comprise a second dielectric material different from the first dielectric material.

Dielectric caps for power and signal line routing

A semiconductor structure comprising a substrate, a first metal layer on top of the substrate, a second metal layer on top of the first metal layer and a dielectric layer adjacent to the second metal layer and at least part of the first metal layer and on top of at least part of the first metal layer. The first metal layer includes a via. The width of the second metal layer is the same as the width of the via of the first metal layer.

Top via patterning using metal as hard mask and via conductor

A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.

Selective ILD deposition for fully aligned via with airgap

A semiconductor device includes a porous dielectric layer including a recessed portion, a conductive layer formed in the recessed portion, and a cap layer formed on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the cap layer.

Semiconductor device including a porous dielectric layer, and method of forming the semiconductor device

A second BEOL layer including a via dielectric layer surrounding a via including an upper metal stud and a lower metal stud separated by a liner, and a magnetic tunnel junction (MTJ) stack aligned above the via. A first back end of line (BEOL) layer including a BEOL dielectric layer surrounding a BEOL metal layer, a second BEOL layer including a via dielectric layer surrounding a via including an upper metal stud and a lower metal stud separated by a liner, a magnetic tunnel junction (MTJ) stack aligned above the via. Forming a via dielectric layer as a second back end of line (BEOL) layer, an opening, a lower metal stud in the opening, a liner on the lower metal stud and on exposed side surfaces of the opening, an upper metal stud in remaining portions of the opening, and forming a magnetic tunnel junction (MTJ) stack aligned above.

Magnetic tunnel junction device with minimum stray field

A semiconductor structure with one or more backside metal layers that include a plurality of portions of a floating metal layer separated by dielectric material from one or more power and ground lines in the backside metal layer. The height of each of the plurality of portions of the floating metal layer in each of the one or more backside metal layers and the distance between adjacent portions of the plurality of portions of the floating metal layer in each of the one or more backside metal layer correlates to the capacitance of each of the one or more backside metal layers.

Backside floating metal for increased capacitance

A method for fabricating a semiconductor device includes forming one or more layers including at least one of a liner and a barrier along surfaces of a first interlevel dielectric (ILD) layer within a trench, after forming the one or more liners, performing a via etch to form a via opening exposing a first conductive line corresponding to a first metallization level, and forming, within the via opening and on the first conductive line, a barrier-less prefilled via including first conductive material.

Barrier-less prefilled via formation

A method for manufacturing a semiconductor device includes forming a first vertical transistor structure in a first device region on a substrate, and forming a second vertical transistor structure in a second device region on the substrate. The first vertical transistor structure includes a first plurality of fins, and the second vertical transistor structure includes a second plurality of fins. A plurality of first source/drain regions are grown from upper portions of the first plurality of fins, and a contact liner layer is formed on the first source/drain regions. The method further includes forming a plurality of first silicide portions from the contact liner layer on the first source/drain regions, and forming a plurality of second silicide portions on a plurality of second source/drain regions extending from upper portions of the second plurality of fins. The second silicide portions have a different composition than the first silicide portions.

Silicide formation for source/drain contact in a vertical transport field-effect transistor

A method for fabricating a semiconductor device including a skip via connection between metallization levels includes subtractively etching first conductive material to form a first via and a skip via on a first conductive line. The first via and the first conductive line are included within a first metallization level. The skip via is used to connect the first metallization level to a third metallization level above a second metallization level. The method further includes forming, on the first via from second conductive material, a second via disposed on a second conductive line. The second via and the second conductive line are included within the second metallization level.

Skip via connection between metallization levels

A method for manufacturing a semiconductor device includes forming a first dielectric layer, and forming a second dielectric layer stacked on the first dielectric layer. In the method, a plurality of conductive lines are formed in the first and second dielectric layers, and the plurality of conductive lines are recessed to form a plurality of openings in the second dielectric layer. The method also includes forming a plurality of dielectric fill layers on the plurality of conductive lines in the plurality of openings. At least one of the plurality of dielectric fill layers is selectively removed with respect to the second dielectric layer to expose a conductive line of the plurality of conductive lines, and a via is formed in place of the selectively removed dielectric fill layer.

Method and structure for forming fully-aligned via

A method for machine learning enhanced optical-based screening for in-line wafer testing includes receiving optical spectra data for a wafer-under-test by performing scatterometry on the wafer-under-test, performing predictive model screening by applying a predictive model based on the optical spectra data, determining whether a device associated with the wafer-under-test is defective based on the predictive model screening, and if the device is determined to be defective, dynamically modifying a yield map associated with the wafer-under-test, including reassigning at least one die.

Machine learning enhanced optical-based screening for in-line wafer testing

Techniques for forming trapezoidal-shaped interconnects are provided. In one aspect, a method for forming an interconnect structure includes: patterning a trench(es) in a dielectric having a V-shaped profile with a rounded bottom; depositing a liner into the trench(es) using PVD which opens-up the trench(es) creating a trapezoidal-shaped profile in the trench(es); removing the liner from the trench(es) selective to the dielectric whereby, following the removing, the trench(es) having the trapezoidal-shaped profile remains in the dielectric; depositing a conformal barrier layer into and lining the trench(es) having the trapezoidal-shaped profile; depositing a conductor into and filling the trench(es) having the trapezoidal-shaped profile over the conformal barrier layer; and polishing the conductor and the conformal barrier layer down to the dielectric. An interconnect structure is also provided.

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Saratoga, NY, United States of America

Huai Huang