Taiwan Semiconductor Manufacturing Comp. Ltd.

Coretronic Corporation

Parabellum Strategic Opportunities Fund LLC

Parabellum Strategic Opportunties Fund LLC

Hua Feng Chen

Min-Yann Hsieh

Kuo-Hua Pan

Jyun-Ming Lin

Joanna Chaw Yane Yin

Wen-Che Tsai

Yu-Jen Chang

Je-Wei Hsu

Chen-Huang Peng

Java Wu

Carlos H Diaz

Zhiqiang Wu

Wen-Hsing Hsieh

Kuei-Shun Chen

Tzer-Min Shen

Shu-Hui Wang

Mu-Chi Chiang

Ya-Yun Cheng

Po-Hsueh Li

Ting-Yun Wu

Jhon Jhy Liaw

Chao-Cheng Chen

Shih-Chi Fu

Yuan-Hsiang Lung

Yan-Tso Tsai

C H Wu

Tsung-Lin Yang

Fan-Chun Lin

Chung-Hung Fang

Ryan Chia-Jen Chen

Chun-Hung Lee

Chia-Chu Liu

Yuan-Sheng Huang

Chi-Kang Chang

Chih-Hsiung Peng

Chiang Mu-Chi

Yen-Hao Lin

Sheng-Yu Chang

Chun-Hsiang Hsu

Wei-Ching Wu

Devices and methods that include for configuring a profile of a liner layer before filling an opening disposed over a semiconductor substrate. The liner layer has a first thickness at the bottom of the opening and a second thickness a top of the opening, the second thickness being smaller that the first thickness. In an embodiment, the filled opening provides a contact structure.

Contact structure of a semiconductor device

A method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an Inter-Layer Dielectric (ILD). The dummy gate stack is in the ILD, and the ILD covers a source/drain region in the semiconductor region. The method further includes removing the dummy gate stack to form a trench in the first ILD, forming a low-k gate spacer in the trench, forming a replacement gate dielectric extending into the trench, forming a metal layer to fill the trench, and performing a planarization to remove excess portions of the replacement gate dielectric and the metal layer to form a gate dielectric and a metal gate, respectively. A source region and a drain region are then formed on opposite sides of the metal gate.

Contact plugs and methods forming same

A semiconductor device includes. A first epi-layer and a second epi-layer are each located in a first region of the semiconductor device. A first dielectric fin is located between the first epi-layer and the second epi-layer. The first dielectric fin has a first dielectric constant. A third epi-layer and a fourth epi-layer are each located in a second region of the semiconductor device. A second dielectric fin is located between the third epi-layer and the fourth epi-layer. The second dielectric fin has a second dielectric constant that is less than the first dielectric constant.

Dielectric fins with different dielectric constants and sizes in different regions of a semiconductor device

Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary interconnect structure includes a conductive feature that includes cobalt and a via disposed over the conductive feature. The via includes a first via barrier layer disposed over the conductive feature, a second via barrier layer disposed over the first via barrier layer, and a via bulk layer disposed over the second via barrier layer. The first via barrier layer includes titanium, and the second via barrier layer includes titanium and nitrogen. The via bulk layer can include tungsten and/or cobalt. A capping layer may be disposed over the conductive feature, where the via extends through the capping layer to contact the conductive feature. In some implementations, the capping layer includes cobalt and silicon.

Vias for cobalt-based interconnects and methods of fabrication thereof

The present disclosure provides an integrated circuit (IC) structure. The IC structure includes first and second fins formed on a semiconductor substrate and laterally separated from each other by an isolation feature, the isolation feature formed of a dielectric material that physically contacts the semiconductor substrate; and a contact feature between the first and second fins and extending into the isolation feature thereby defining an air gap vertically between the isolation feature and the contact feature, the dielectric material of the isolation feature extending from the semiconductor substrate to the contact feature.

FinFET structure with controlled air gaps

Method of fabricating a semiconductor device having a liner layer with a configured profile

Embodiments of the disclosure provide a semiconductor device including a substrate, an insulating layer formed over the substrate, a plurality of fins formed vertically from a surface of the substrate, the fins extending through the insulating layer and above a top surface of the insulating layer, a gate structure formed over a portion of fins and over the top surface of the insulating layer, a source/drain structure disposed adjacent to opposing sides of the gate structure, the source/drain structure contacting the fin, a dielectric layer formed over the insulating layer, a first contact trench extending a first depth through the dielectric layer to expose the source/drain structure, the first contact trench containing an electrical conductive material, and a second contact trench extending a second depth into the dielectric layer, the second contact trench containing the electrical conductive material, and the second depth is greater than the first depth.

FinFET isolation structure and method for fabricating the same

Semiconductor device having a liner layer with a configured profile

Growing community of inventors

Hsinchu, Taiwan

Hua Feng Chen