Industrial Technology Research Institute

Etron Technology, Inc.

Hu H Chao

Hsiao-Chin Tuan

Denny Duan-Lee Tang

Hsiang-Ming J Chou

A buried channel lateral quasi-unipolar transistor having low flicker or 1/f noise has a bulk region that forms the base of the buried quasi-unipolar transistor. A drain region is implanted into the bulk region to form a drain/collector. A source region is placed at a distance from the drain region and is implanted in the bulk region to form a source/emitter. A channel layer is implanted in the bulk region between the source region and the drain region to provide a low resistivity conduction channel between the drain/collector and the source/emitter. A gate oxide is placed on the surface of the semiconductor substrate immediately above the channel layer. Then a gate electrode of a conductive material such as polycrystalline silicon doped to with a material having a conductivity opposite that of the source/drain deposited on the gate oxide above the channel region. A biasing voltage source connected between the gate electrode and the bulk region to lower a built-in voltage of the quasi-unipolar transistor. The buried channel lateral quasi-unipolar transistor further may have an overlayer implanted between the channel layer and the surface of the semiconductor substrate to form the buried channel layer rather than at the surface of the semiconductor substrate. The buried channel lateral quasi-unipolar transistor may be placed in a diffusion well into which a bulk region is implanted.

Buried channel quasi-unipolar transistor

A method of forming a silicon oxide isolation region on the surface of a silicon wafer consisting of a thin layer of silicon oxide on the wafer, a layer of impurity-doped polysilicon, and a layer of silicon nitride. The oxidation mask is formed by patterning the silicon nitride layer and at least a portion of the doped polysilicon layer. The silicon oxide field isolation region is formed by subjecting the structure to a thermal oxidation ambient. The oxidation mask is removed in one continuous etching step using a single etchant, such as phosphoric acid which etches the silicon nitride and polysilicon layers at substantially the same rate to complete the formation of the isolation region without pitting the monocrystalline substrate.

Fabrication method to produce pit-free polysilicon buffer local

The method of forming an integrated circuit field effect transistor having a gate electrode, source and drain elements with buried contacts to a silicon substrate. A gate silicon oxide layer is formed on the silicon substrate. An in-situ doped layer of polysilicon is formed over the gate silicon oxide layer. An opening is formed in the doped polysilicon layer and the silicon oxide layer to the silicon substrate at the location of the buried contacts. A layer of undoped polysilicon is deposited over the doped polysilicon layer and in the opening to the silicon substrate. Doping by ion implantation of the undoped polysilicon layer is done to form a doped polysilicon gate electrode/buried contact layer. The polysilicon gate electrode/buried contact layer is patterning and etching to form the gate electrode of said transistor and buried contact layer. The source and drain regions are implanted using said polysilicon gate electrode pattern as a mask. The structure is heated to form the buried contact to at least one of the source and drain regions. Alternatively, a contact to an existing device region within the substrate may be contacted using a similar multiple layer polysilicon method.

Growing community of inventors

Hsinchu, Taiwan

Hu H Chao