Shanghai Huali Microelectronics Corporation

Hsusheng Chang

Yukun Lv

Jian Ding

Fang Wei

Zaifeng Tang

Chao Fang

Zhi Jun Wang

Lijun Chen

Yu Ren

Jingxun Fang

YungChieh Fan

Peng Liu

Qiyan Feng

WenLiang Li

Chenming Zhang

Han Chen

Zhihao Chu

Chuan Ren

The invention disclosed a method for forming high aspect ratio patterning structure. Firstly, forming a dielectric film ashing stop layer, a first photoresist layer, a first hard mask layer and a second photoresist layer on a semiconductor substrate in turn. A second hard mask layer having a high etch selectivity ratio with the first photoresist layer is formed on top surface and sidewall of the pattern by utilizing a low temperature chemical vapor deposition process, which can be a protect for the pattern sidewall during the later etching process of the first photoresist layer. So, the cone-shaped or the bowling-shaped photoresist morphology caused by plasma bombardment can be avoided. Therefore, the problems of the insufficient of selectivity ratio, burrs at the edge of the pattern and larger critical dimension can be solved, and the implanted ions can be well distributed according to the design of the device.

Method for forming high aspect ratio patterning structure

An apparatus for detecting the flatness of a top surface of a wafer includes a plurality of detector elements, a metal sink and a plurality of injection pipes. Each detector element comprises: a metal tube body, jet pipes, a light receiver and a light emitter. The method comprises: injecting ultra-pure water into the detector elements by injection pipes; emitting parallel beams along an upward-oblique direction, a preset Angle &#x3b8; being formed between the beams and the vertical direction. The radiated beams above the water surface are incident on a receiver. The intensity of the beams received by the light receiver is used to calculate the height of the detecting point of the surface of the silicon wafer to determine the flatness condition of the wafer surface. The flatness of the photo-resist covered on the wafer surface can also be accurately measured by this method.

Apparatus for detecting the flatness of wafer and the method thereof

A method for etching a polysilicon gate is disclosed, wherein the polysilicon gate includes an undoped polysilicon portion and a doped polysilicon portion that is situated on the undoped polysilicon portion. The method includes: obtaining a thickness of the undoped polysilicon portion and a thickness of the doped polysilicon portion by using an optical linewidth measurement device; and etching the undoped polysilicon portion and the doped polysilicon portion by using two respective steps with different parameters, respective etching time for the undoped polysilicon portion and the doped polysilicon portion of every wafer being adjusted in real time by using an advanced process control system. This method enables the doped and undoped polysilicon portions of each polysilicon gate on every wafer to have substantially consistent profiles between each other.

Method for etching polysilicon gate

A method of layout pattern modification includes the following steps: step 1: performing an OPC process on a layout containing a plurality of square patterns to obtain a plurality of post-OPC patterns in correspondence with the plurality of square patterns; step 2: performing a manufacturing rule check on each of the plurality of post-OPC patterns to identify, from the plurality of post-OPC patterns, one or more post-OPC patterns violating the manufacturing rule; and step 3: rotating at least one of the one or more post-OPC patterns violating the manufacturing rule; and step 4: performing a manufacturing rule check on each of the rotated and non-rotated post-OPC patterns, if no post-OPC pattern violating the manufacturing rule is identified, finishing the process; otherwise, if one or more post-OPC patterns violating the manufacturing rule are identified, continuing to perform step 3 and step 4.

Layout pattern modification method

An optical proximity correction (OPC) method is disclosed, in which original design patterns are first grouped into a first group and a second group, wherein each pattern of the first group has a size greater than a size of any pattern of the second group. Next, a simple OPC model and a complex OPC model are individually established for the two groups using different numbers of convolution kernels. After that, the simple OPC model and the complex OPC model are combined together to generate a hybrid OPC model which is thereafter used to perform an OPC treatment on the original design patterns. This method is capable of shortening the OPC processing time and increasing the flexibility in utilizing OPC software and hardware resources.

Optical proximity correction method based on hybrid simulation model

A dummy wafer structure and a method of forming the same are disclosed. The dummy wafer structure includes: a silicon substrate; a silicon nitride layer over the silicon substrate; and a silicon dioxide layer over the silicon nitride layer. The method includes: a first step of forming a silicon nitride layer over a silicon substrate so as to form a silicon-silicon nitride structure; and a second step of forming a silicon dioxide layer over the silicon-silicon nitride structure obtained in the first step so as to form a silicon-silicon nitride-silicon dioxide structure. Dummy wafers with this special structure are able to avoid deposition rate inconsistency in a polysilicon deposition process and are capable of avoiding conventional dummy wafers' adverse effect on deposit layer thicknesses of process wafers and hence providing the process wafers with deposit layers having a high inter-wafer uniformity.

Dummy wafer structure and method of forming the same

The present invention discloses a method for reducing the morphological difference between N-doped and undoped poly-silicon gates after etching, comprising the following sequential steps: depositing a hard mask layer on a substrate template having N-doped poly-silicon and undoped poly-silicon to form an N-doped poly-silicon hard mask layer and an undoped poly-silicon hard mask layer respectively, and etching the undoped poly-silicon hard mask layer to make a thickness difference between the N-doped poly-silicon hard mask layer and the undoped poly-silicon hard mask layer; depositing an anti-reflection layer, and etching according to a predetermined pattern until exposing the N-doped poly-silicon, wherein when the N-doped poly-silicon is exposed, the undoped poly-silicon is etched to a certain degree; and removing residuals on the surface of the above formed structure, and etching to form an N-doped poly-silicon gate and an undoped poly-silicon gate, respectively.

Method for reducing morphological difference between N-doped and undoped polysilicon gates after etching

The present invention disclosed an algorithm of Cu interconnect dummy inserting, including: divide the surface of semiconductor chip into several square windows with an area of A, each of which is non-overlap; perform a logic operation on each square window; and divide the window into two parts: {circle around (1)} the area to-be-inserted; {circle around (2)} the non-inserting area; determine the metal density of the dummy pattern that should be inserted to each square window and the line width; determine the dummy pattern that should be inserted to the windows according to the metal density, line width, the pre-set dummy pattern and the layouting rules. The beneficial effects of the present invention is: avoided the shortcomings of fill density maximization in the rule-based filling method by using reasonable metal density and line width. And with a combination of the influence of line width and density to the copper plating process and chemical mechanical polishing morphology in model-based filling method, it can achieve a better planarization effect.

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Shanghai, China

Hsusheng Chang