Industrial Technology Research Institute

Hsun Yu

Shih-Hsien Wu

Chang-Chih Liu

Peng-Shu Chen

A chip stacking structure including a plurality of microbump structures, a plurality of first substrates, at least one first space layer, a plurality of second substrates and at least one second space layer is provided. The first substrates are stacked upon each other by a portion of the microbump structures, and each of the first substrates includes at least one first redistribution layer. The first space layer is located between the stacked first substrates. The second substrates are stacked on at least one of the first substrates by another portion of the microbump structures, and each of the second substrates includes at least one second redistribution layer. The second space layer is located between the stacked first and second substrates. The first redistribution layers, the second redistribution layers and the microbump structures form a plurality of impedance elements, and the impedance elements provide a specific oscillation frequency.

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Hsinchu County, Taiwan

Hsun Yu