Taiwan Semiconductor Manufacturing Comp. Ltd.

Hsun-Ying Huang

Kuo-Cheng Lee

Hsin-Chi Chen

Yun-Wei Cheng

Chun-Hao Chou

Yen-Liang Lin

Chia-Yu Wei

Dun-Nian Yaung

Jen-Cheng Liu

Min-Feng Kao

Jeng-Shyan Lin

Yin-Chieh Huang

Yung-Cheng Chang

Wei-Chih Weng

Chih-Ming Lee

Cheng-Yuan Li

Chia-Chi Hsiao

Ching-Hung Kao

Shih-Hsun Hsu

Fu-Cheng Chang

Ping-Hao Lin

Chia-Pin Cheng

Yu-Yang Shen

Shou-Shu Lu

Yu Ting Kao

Chun-Wei Chia

Chao-Ching Chang

Yi-Hsing Chu

Shang-Yen Wu

Chun-Mao Chiu

Tsung-Wei Huang

You Che Chuang

Hsin-Jung Huang

Shou Shu Lu

Chih-An Yang

Hung-Wei Ho

Wen-I Hsu

Chi-Hsun Hsieh

Jia-Ren Chen

Yung-Fu Yeh

Juan-Lin Chen

I-Chang Lin

Jin-Hong Cho

Cheng-Tsung Chen

Yu-Ping Chen

Chi-Yuan Liang

Horng-Daw Shen

Yu-Ting Kao

Ching-Chun Wang

Tzu-Hsuan Hsu

Hsing-Chih Lin

Hsien-Liang Meng

Chih-Ho Tai

Bo-Chang Su

Kuo-cheng Lee

A semiconductor device includes a plurality of isolation structures, wherein each isolation structure of the plurality of isolation structures is spaced from an adjacent isolation structure of the plurality of isolation structures. The semiconductor device further includes a gate structure. The gate structure includes a first sidewall and a second sidewall angled with respect to the first sidewall. The gate structure further includes a first surface extending between the first sidewall and the second sidewall, wherein a dimension of the gate structure in a first direction is less than a dimension of each of the plurality of isolation structures in the first direction.

Wide channel semiconductor device

The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method includes forming a first dielectric bonding layer over a first dielectric structure, which is disposed on a first substrate and surrounds a first plurality of interconnects. The first dielectric bonding layer is patterned to form a first recess exposing one of the first plurality of interconnects. A first conductive bonding segment is formed within the first recess. A second dielectric bonding layer is formed over a TSV extending through a second substrate. The second dielectric bonding layer is patterned to form a second recess exposing the TSV. A second conductive bonding segment is formed within the second recess. The first substrate is bonded to the second substrate along an interface comprising dielectric and conductive regions. The conductive region includes a conductive interface between the first and second conductive bonding segments.

Stacked substrate structure with inter-tier interconnection

An image sensor device is provided. The image sensor device includes a substrate having a front surface, a back surface, and a light-sensing region. The image sensor device includes a first isolation structure extending from the front surface into the substrate. The first isolation structure surrounds a first portion of the light-sensing region, the first isolation structure has an etch stop layer, the etch stop layer has an end portion, and the end portion has an H-like shape. The image sensor device includes a second isolation structure extending into the substrate from the back surface to the end portion. The second isolation structure surrounds a second portion of the light-sensing region.

Image sensor device

The present disclosure relates to a semiconductor image sensor with improved quantum efficiency. The semiconductor image sensor can include a semiconductor layer having a first surface and a second surface opposite of the first surface. An interconnect structure is disposed on the first surface of the semiconductor layer, and radiation-sensing regions are formed in the semiconductor layer. The radiation-sensing regions are configured to sense radiation that enters the semiconductor layer from the second surface and groove structures are formed on the second surface of the semiconductor layer.

Image sensor with improved quantum efficiency surface structure

An image sensor device includes a semiconductor substrate, a radiation sensing member, a shallow trench isolation, and a color filter layer. The radiation sensing member is in the semiconductor substrate. An interface between the radiation sensing member and the semiconductor substrate includes a direct band gap material. The shallow trench isolation is in the semiconductor substrate and surrounds the radiation sensing member. The color filter layer covers the radiation sensing member.

The present disclosure relates to a CMOS image sensor, and an associated method of formation. In some embodiments, the CMOS image sensor comprises a substrate and a transfer gate disposed from a front-side surface of the substrate. The CMOS image sensor further comprises a photo detecting column disposed at one side of the transfer gate within the substrate. The photo detecting column comprises a doped sensing layer comprising one or more recessed portions along a circumference of the doped sensing layer in parallel to the front-side surface of the substrate. By forming the photo detecting column with recessed portions, a junction interface is enlarged compared to a previous p-n junction interface without recessed portions, and thus a full well capacity of the photodiode structure is improved.

CMOS image sensor having indented photodiode structure

In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first plurality of interconnects within a first inter-level dielectric (ILD) structure disposed along a first side of a first substrate. A conductive pad is arranged along a second side of the first substrate. A first through-substrate-via (TSV) physically contacts an interconnect of the first plurality of interconnects and a first surface of the conductive pad. A second plurality of interconnects are within a second ILD structure disposed on a second substrate. A second TSV extends from an interconnect of the second plurality of interconnects to through the second substrate. A conductive bump is arranged on a second surface of the conductive pad opposing the first surface. The second TSV has a greater width than the first TSV.

Integrated chip for standard logic performance improvement having a back-side through-substrate-via and method for forming the integrated chip

An image sensor including a semiconductor substrate, a plurality of color filters, a plurality of first lenses and a second lens is provided. The semiconductor substrate includes a plurality of sensing pixels arranged in array, and each of the plurality of sensing pixels respectively includes a plurality of image sensing units and a plurality of phase detection units. The color filters at least cover the plurality of image sensing units. The first lenses are disposed on the plurality of color filters. Each of the plurality of first lenses respectively covers one of the plurality of image sensing units. The second lens is disposed on the plurality of color filters and the second lens covers the plurality of phase detection units.

Image sensor including light shielding layer and patterned dielectric layer

A semiconductor device structure, along with methods of forming such, are described. The structure includes a substrate having one or more devices formed thereon, one or more bonding pads disposed over the substrate, and a first passivation layer disposed over the one or more bonding pads. The first passivation layer includes a first passivation sublayer having a first dielectric material, a second passivation sublayer disposed over the first passivation sublayer, and the second passivation sublayer has a second dielectric material different from the first dielectric material. The first passivation layer further includes a third passivation sublayer disposed over the second passivation sublayer, and the third passivation sublayer has a third dielectric material different from the second dielectric material. At least two of the first, second, and third passivation sublayers each includes a nitride.

Semiconductor device structure and methods of forming the same

A semiconductor structure includes a first transistor comprising a first gate structure over a first active region in a substrate. The semiconductor structure further includes a second active region in the substrate. The semiconductor structure further includes a first butted contact. The first butted contact includes a first portion extending in a first direction and overlapping the second active region, and a second portion extending from the first portion, wherein the second portion directly contacts each of a top surface and a sidewall of the first gate structure.

Semiconductor device having a butted contact and method of forming

A semiconductor structure is provided. The semiconductor structure includes a first semiconductor device. The semiconductor structure includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first oxide layer formed below the a first substrate, a first bonding layer formed below the first oxide layer, and a first bonding via formed through the first bonding layer and the first oxide layer. The second semiconductor device includes a second oxide layer formed over a second substrate, a second bonding layer formed over the second oxide layer, and a second bonding via formed through the second bonding layer and the second oxide layer. The semiconductor structure also includes a bonding structure between the first substrate and the second substrate, and the bonding structure includes the first bonding via bonded to the second bonding via.

Semiconductor structure

An image sensor device includes a semiconductor substrate, a radiation sensing member, a device layer, and a color filter layer. The semiconductor substrate has a photosensitive region and an isolation region surrounding the photosensitive region. The radiation sensing member is embedded in the photosensitive region of the semiconductor substrate. The radiation sensing member has a material different from a material of the semiconductor substrate, and an interface between the radiation sensing member and the isolation region of the semiconductor substrate includes a direct band gap material. The device layer is under the semiconductor substrate and the radiation sensing member. The color filter layer is over the radiation sensing member and the semiconductor substrate.

An image sensor device is provided. The image sensor device includes a substrate having a front surface, a back surface, and a light-sensing region. The image sensor device includes a first isolation structure extending from the front surface into the substrate. The first isolation structure surrounds a first portion of the light-sensing region, and the first isolation structure has a first end portion in the substrate. The image sensor device includes a second isolation structure extending from the back surface into the substrate. The second isolation structure surrounds a second portion of the light-sensing region, the second isolation structure has a second end portion in the substrate, and the second end portion of the second isolation structure is closer to the front surface of the substrate than the first end portion of the first isolation structure.

The present disclosure is directed to anchor structures and methods for forming anchor structures such that planarization and wafer bonding can be uniform. Anchor structures can include anchor layers formed on a dielectric layer surface and anchor pads formed in the anchor layer and on the dielectric layer surface. The anchor layer material can be selected such that the planarization selectivity of the anchor layer, anchor pads, and the interconnection material can be substantially the same as one another. Anchor pads can provide uniform density of structures that have the same or similar material.

Anchor structures and methods for uniform wafer planarization and bonding

Growing community of inventors

Tainan, Taiwan

Hsun-Ying Huang