Taiwan Semiconductor Manufacturing Comp. Ltd.

Hsun-Chung Kuang

Hai-Dang Trinh

Cheng-Yuan Tsai

Bi-Shen Lee

Sheng-Chau Chen

Cheng-Tai Hsiao

Fa-Shen Jiang

Hsing-Lien Lin

Yi Yang Wei

Ping-Yin Liu

Lan-Lin Chao

Chin-Wei Liang

Chia-Shiung Tsai

Xiaomeng Chen

Xin-Hua Huang

Ming-Tung Wu

Hsia-Wei Chen

Yen-Chang Chu

Tung-He Chou

Yao-Wen Chang

Zhen Yu Guan

Yuan-Chih Hsieh

Hung-Hua Lin

Chun-Kai Lan

Harry-Hak-Lay Chuang

Yeur-Luen Tu

Ru-Liang Lee

Sheng-Chan Li

Kuei-Hung Shen

Tzu-Yu Lin

Ching Ju Yang

Der-Chyang Yeh

Chung-Yi Yu

Ming Chyi Liu

Chen-Jong Wang

Bruce C S Chou

Chih-Ping Chao

Jung-Kuo Tu

Tsung-Te Chou

Yi-Yang Wei

Hsien Hua Shen

Alexander Kalnitsky

Yuan-Tai Tseng

Feng-Jia Shiu

Chia-Hua Lin

Hua-Chou Tseng

Ching-Sen Kuo

Yu-Hsing Chang

Min-Ying Tsai

Tzu-Chung Tsai

Wei-Chieh Huang

Jieh-Jang Chen

Hsin-Yu Lai

Cheng-Che Chung

Tsai-Ming Huang

Chia-Wei Hu

Li-Wen Chang

Sheng-Wen Fu

Bi-shen Lee

Yu-Min Chen

Various embodiments of the present disclosure are directed towards a memory device. The memory device has a first transistor having a first source/drain and a second source/drain, where the first source/drain and the second source/drain are disposed in a semiconductor substrate. A dielectric structure is disposed over the semiconductor substrate. A first memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the first memory cell has a first electrode and a second electrode, where the first electrode of the first memory cell is electrically coupled to the first source/drain of the first transistor. A second memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the second memory cell has a first electrode and a second electrode, where the first electrode of the second memory cell is electrically coupled to the second source/drain of the first transistor.

Circuit design and layout with high embedded memory density

A Deep Trench Isolation (DTI) structure is disclosed. The DTI structures according to embodiments of the present disclosure include a composite passivation layer. In some embodiments, the composite passivation layer includes a hole accumulation layer and a defect repairing layer. The defect repairing layer is disposed between the hole accumulation layer and a semiconductor substrate in which the DTI structure is formed. The defect repairing layer reduces lattice defects in the interface, thus, reducing the density of interface trap (DIT) at the interface. Reduced density of interface trap facilitates strong hole accumulation, thus increasing the flat band voltage. In some embodiments, the hole accumulation layer according to the present disclosure is enhanced by an oxidization treatment.

Deep trench isolation structure and methods for fabrication thereof

Various embodiments of the present disclosure are directed towards an integrated chip including a first conductive structure over a substrate. A data storage structure overlies the first conductive structure. The data storage structure comprises a first dielectric layer on the first conductive structure and a second dielectric layer on the first dielectric layer. The first dielectric layer comprises a dielectric material and a first dopant having a concentration that changes from a top surface of the first dielectric layer in a direction towards the first conductive structure. A second conductive structure overlies the data storage structure.

Resistive memory cell with switching layer comprising one or more dopants

A method includes forming a bottom electrode layer, and depositing a first ferroelectric layer over the bottom electrode layer. The first ferroelectric layer is amorphous. A second ferroelectric layer is deposited over the first ferroelectric layer, and the second ferroelectric layer has a polycrystalline structure. The method further includes depositing a third ferroelectric layer over the second ferroelectric layer, with the third ferroelectric layer being amorphous, depositing a top electrode layer over the third ferroelectric layer, and patterning the top electrode layer, the third ferroelectric layer, the second ferroelectric layer, the first ferroelectric layer, and the bottom electrode layer to form a Ferroelectric Random Access Memory cell.

FeRAM with laminated ferroelectric film and method forming same

In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a lower electrode structure disposed over one or more interconnects. The one or more interconnects are arranged within a lower inter-level dielectric (ILD) structure over a substrate. A barrier is arranged along a lower surface of the lower electrode structure. The barrier separates the lower electrode structure from the one or more interconnects. An amorphous initiation layer is over the lower electrode layer and a ferroelectric material is on the amorphous initiation layer. The ferroelectric material has a substantially uniform orthorhombic crystalline phase. An upper electrode is over the ferroelectric material.

Interface film to mitigate size effect of memory device

In some embodiments, the present disclosure relates to a method that includes forming a dielectric layer over a substrate and patterning the dielectric to form an opening in the dielectric layer. Further, a conductive material is formed within the opening of the dielectric layer. A planarization process is performed to remove portions of the conductive material arranged over the dielectric layer thereby forming a conductive feature within the opening of the dielectric layer. An anti-oxidation layer is formed on upper surfaces of the conductive feature, and then, the anti-oxidation layer is removed.

Anti-oxidation layer to prevent dielectric loss from planarization process

A method of depositing a layer on a semiconductor workpiece is disclosed. The method includes placing the semiconductor workpiece on a wafer chuck in a processing chamber, introducing a first precursor into the processing chamber, introducing a second precursor into the processing chamber, and while the second precursor is in the processing chamber, applying radiation to the semiconductor workpiece, whereby a surface of the semiconductor workpiece is heated. The method also includes, while the second precursor is in the processing chamber, applying a voltage bias to the wafer chuck.

Remote plasma ultraviolet enhanced deposition

A memory device includes a field effect transistor and a variable-capacitance capacitor. A gate structure includes a gate dielectric and an intermediate electrode. The variable-capacitance capacitor includes a lower capacitor plate comprising the intermediate electrode, an upper capacitor plate comprising a control gate electrode, and a variable-capacitance node dielectric and including an electrical-field-programmable metal oxide material. The electrical-field-programmable metal oxide material provides a variable effective dielectric constant, and a data bit may be stored as a dielectric state of the variable-capacitance node dielectric in the memory device. The variable-capacitance node dielectric provides reversible electrical field-dependent resistivity modulation, or reversible electrical field-dependent movement of metal atoms therein.

Threshold voltage-modulated memory device using variable-capacitance and methods of forming the same

A method of fabricating a semiconductor device includes receiving a device substrate; forming an interconnect structure on a front side of the device substrate; and etching a recess into a backside of the device substrate until a portion of the interconnect structure is exposed. The recess has a recess depth and an edge of the recess is defined by a sidewall of the device substrate. A conductive bond pad is formed in the recess, and a first plurality of layers cover the conductive bond pad, extend along the sidewall of the device substrate, and cover the backside of the device substrate. The first plurality of layers collectively have a first total thickness that is less than the recess depth. A first chemical mechanical planarization is performed to remove portions of the first plurality of layers so remaining portions of the first plurality of layers cover the conductive bond pad.

Bond pad structure for bonding improvement

A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate, a first dielectric layer, an etching stop layer, a second dielectric layer, a conductive via, and a data storage structure. The first dielectric layer is disposed on the substrate. The etching stop layer is disposed on the first dielectric layer. The second dielectric layer is disposed on the etching stop layer. The first dielectric layer, the etching stop layer, and the second dielectric layer collectively define an opening. The conductive via is disposed in the opening. The data storage structure is disposed on the conductive via.

Semiconductor device and method of manufacturing the same

Some embodiments relate to a semiconductor structure. The semiconductor structure includes a conductive structure over a semiconductor substrate. A first dielectric layer is over the conductive structure. A second dielectric layer is over the first dielectric layer. An interconnect structure is over the conductive structure and disposed in the first and second dielectric layers. The interconnect structure has a protrusion in direct contact with a sidewall of the conductive structure. The interconnect structure comprises an interconnect liner surrounding a conductive interconnect body. A sidewall spacer is disposed on the sidewall of the conductive structure.

Conductive structure connection with interconnect structure

An interfacial layer is provided that binds a hydrophilic interlayer dielectric to a hydrophobic gap-filling dielectric. The hydrophobic gap-filling dielectric extends over and fill gaps between devices in an array of devices disposed between two metal interconnect layers over a semiconductor substrate and is the product of a flowable CVD process. The interfacial layer provides a hydrophilic upper surface to which the interlayer dielectric adheres. Optionally, the interfacial layer is also the product of a flowable CVD process. Alternatively, the interfacial layer may be silicon nitride or another dielectric that is hydrophilic. The interfacial layer may have a wafer contact angle (WCA) intermediate between a WCA of the hydrophobic dielectric and a WCA of the interlayer dielectric.

Techniques to inhibit delamination from flowable gap-fill dielectric

A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.

Integrate rinse module in hybrid bonding platform

A pad conditioner for conditioning a polishing surface of a polishing pad includes a conditioning disk, a disk holder, and a disk arm. The conditioning disk includes a substrate plate and at least two abrasive segments. The conditioning disk includes at least one channel by which debris and spent slurry may be evacuated. The abrasive segments are on a surface of the substrate plate, and form at least one channel segment therebetween. Each channel segment extends from about the center of the surface to substantially the outer rim of the substrate plate. The disk holder to which the conditioning disk is mounted includes a through hole. The disk arm to which the conditioning disk is mounted includes an opening in fluid communication with the at least one channel segment via the through hole for evacuating the debris and spent slurry by a vacuum module.

Conditioner disk, chemical mechanical polishing device, and method

Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a bottom electrode over a substrate. A data storage structure is formed on the bottom electrode. The data storage structure comprises a first dopant with a first atomic percent and a second dopant with a second atomic percent. The first atomic percent is different from the second atomic percent. A top electrode is formed on the data storage structure.

Multi-doped data storage structure configured to improve resistive memory cell performance

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Hsinchu, Taiwan

Hsun-Chung Kuang