United Microelectronics Corp.

Macronix International Co., Ltd.

Winbond Electronics Corporation

United Integrated Circuits Corp.

Hsueh-Hao Shih

Tri-Rung Yew

Kuang-Chao Chen

Juan-Yuan Wu

Water Lur

Gwo-Shii Yang

Kuen-Chu Chen

Yu-Shan Tai

H T Yang

Chih-Chien Liu

Chien-Hung Zordius Chen

Wen-Kuan Yeh

Szu-Yu Wang

Ling-Wuu Yang

Mu-Chun Wang

Yung-Tai Hung

Meng-Ping Chuang

Michael W C Huang

Yuhturng Liu

Alan Cheng

Hung-Wei Liu

Jing-Hua Chiang

Chin Hsiang Lin

Chin-Wei Liao

A semiconductor structure with a through silicon via includes a substrate having a front side and a back side. The through silicon via penetrates the substrate. A device is disposed on the front side of the substrate. Numerous dielectric layers cover the front side. A first test pad for testing the device is disposed on the front side of the substrate. A second test pad for testing the through silicon via is disposed on the back side of the substrate. A method of fabricating and testing the semiconductor structure is also provided.

Semiconductor structure with through silicon via and method for fabricating and testing the same

A semiconductor memory device having a memory cell including a plurality of memory cells, a first P-type well region, a second P-type well region, and an N-type well region disposed between the first P-Type well region and the second P-type well region. The semiconductor memory element defines a plurality of first regions, a plurality of second regions, a plurality of third regions, and a plurality of fourth regions, and each first region includes the memory cell. Each second region, each third region and each fourth region include a voltage contact to provide a voltage to the first P-type well region, the second P-type well region, and the N-type well region. The first region to the fourth region do not overlap with each other.

Semiconductor memory device

A manufacturing method of a nanowire structure includes the following steps. A fin and a shallow trench isolation (STI) are formed on a substrate. A first patterned insulation layer is formed on an exposed upper part of the fin. The STI is then recessed for exposing a lower part of the fin. A second patterned insulation layer is formed in second regions for covering the first patterned insulation layer and the exposed part of the fin. The lower part of the fin is then removed for forming an upper fin and a lower fin in a first region. The STI is further recessed for exposing a portion of the lower fin and a portion of the fin in the second regions. The first patterned insulation layer on the first region is removed, and the upper fin is converted into a first nanowire.

Nanowire structure and manufacturing method thereof

A semiconductor capacitor is includes a substrate, a plurality of odd layers formed on the substrate, and a plurality of even layers formed on the substrate. Each odd layer includes a plurality of first odd fingers and a first odd terminal electrically connected thereto, and a plurality of second odd fingers and a second odd terminal electrically connected thereto. Each even layer includes a plurality of first even fingers and a first even terminal electrically connected thereto, and a plurality of second even fingers and a second even terminal electrically connected thereto. The semiconductor capacitor further includes at least a first odd connecting structure electrically connecting the first odd terminals, at least a second odd connecting structure electrically connecting the second odd terminals, at least a first even connecting structure electrically connecting the first even terminals, and at least a second even connecting structure electrically connecting the second even terminals.

Semiconductor capacitor

A method for fabricating gate oxide includes a dilute wet oxidation process with additional nitrogen and moisture and an annealing process with a nitrogen base gas, wherein the volume of additional nitrogen is about6-126-20times of the volume of the additional moisture. The method according to the invention improves the electrical quality of the gate oxide by raising the Qand by reducing the leakage current of the gate oxide.

Method for fabricating gate oxide

The present invention is directed to forming memory wordlines having a relatively lower sheet resistance. In one embodiment, a control-gate poly layer including a first and a second poly-Si portion is deposited. a The first poly-Si portion is deposited on a semiconductor substrate using a first precursor gas flow rate. A The second poly-Si portion is deposited on the first poly-Si portion using a second precursor gas flow rate, where the second precursor flow rate higher than the first precursor gas flow rate. A tungsten silicide layer is then deposited. A wordline is formed from a stacked film of the control-gate poly layer and tungsten silicide layer. The control-gate poly layer and tungsten silicide layer are then patterned to form a gate electrode, and a implantation process is made, after or before, forming the tungsten silicide layer.

Methods for reducing wordline sheet resistance

A fabrication method for a shallow trench isolation region is described. A part of the trench is filled with a first insulation layer, followed by performing a surface treatment process to form a surface treated layer on the surface of a part of the first insulation layer. The surface treated layer is then removed, followed by forming a second insulation layer on the first insulation layer and filling the trench to form a shallow trench isolation region. Since a part of the trench is first filled with the first insulation layer, followed by removing a portion of the first insulation layer, the aspect ratio of the trench is lower before the filling of the second insulation in the trench. The adverse result, such as, void formation in the shallow trench isolation region due to a high aspect ratio, is thus prevented.

Fabrication method for shallow trench isolation region

A method of fabricating a flash memory device is provided. First, a substrate partitioned into a memory cell region and a peripheral circuit region is provided. A tunnel dielectric layer is formed over the memory cell region and a liner layer is formed over the peripheral circuit region. Thereafter, a patterned gate conductive layer is formed over the substrate. An inter-gate dielectric layer and a passivation layer are sequentially formed over the substrate. The passivation layer, the inter-gate dielectric layer, the gate conductive layer and the liner layer over the peripheral circuit region are removed. A gate dielectric layer is formed over the peripheral circuit region while the passivation layer over the memory cell region is converted into an oxide layer. Another conductive layer is formed over the substrate. The conductive layer, the oxide layer, the inter-gate dielectric layer and the gate conductive layer over the memory cell region are patterned to form a memory gate. The second conductive layer over the peripheral circuit region is similarly patterned to form a gate.

Method of manufacturing flash memory

A chemical mechanical polishing to polish a substrate having a layer to be polished thereon is described. A pre-polishing process is performed using a softer polishing pad to remove partially raised parts of the layer to be polished before conducting a polishing process using a harder polishing pad. Since the first polishing pad is flexible, porous and with low density, the first polishing pad can be deformed to increase contact areas between the first polishing pad and the raised part of the layer to be polished, and the abrasives are embedded easily in holes of the surface of the first polishing pad. Ultimately, the layer to be polished can be polished directly during the pre-polishing process. Therefore, the processing time is reduced, the consumption of the slurry is decreased and the process cost can be cut down substantially.

Polishing pad and process of chemical mechanical use thereof

A method of manufacturing a semiconductor device including providing a first layer, forming a layer of stacked oxide-nitride-oxide layer over the first layer, depositing a first silicon layer over the layer of stacked oxide-nitride-oxide layer, providing a layer of photoresist over the first silicon layer, patterning and defining the photoresist layer, etching the first silicon layer and stacked oxide-nitride-oxide layer unmasked by the photoresist, removing the photoresist layer, providing a cleaning solution to the stacked oxide-nitride-oxide layer with the first silicon layer as a mask, and depositing a second layer of polysilicon over the first silicon layer to form a combined silicon layer.

Method for removing fences without reduction of ONO film thickness

A method for improving the quality of a deposited layer over a silicon substrate in a selective deposition where the silicon substrate has a native oxide layer thereon. A plasma reaction using a halogen compound as a reactive agent is performed so that the native oxide layer is transformed into a silicon halide layer and then removed at low pressure. A layer of the desired material is formed over the native oxide free silicon substrate surface by selective deposition.

Method of improving deposition

A method for forming borderless contact is disclosed. The method includes providing a substrate with active areas and a trench isolation region in which the active areas are silcide. Then, the substrate is nitridized such that a titanium nitride layer is formed on the active areas and a silicon oxynitride is formed on the trench isolation region. A dielectric layer is deposited on the substrate and an opening is etched in the dielectric layer in which the opening overlies both a portion of the trench isolation region and a portion of the active area.

Method of forming borderless contact

A method of fabricating a shallow trench isolation structure is described. A preserve layer is formed on a substrate. A trench is formed in the substrate and the preserve layer. An oxide layer is formed over the substrate to fill the trench. A wet densification step is performed in a moist environment. A planarization step is performed until the preserve layer is exposed. A shallow trench isolation structure is formed.

Method of fabricating shallow trench isolation structure

A method for forming a gate on a substrate for manufacturing semiconductor devices is described. The present method comprises the step of providing a gate oxide layer on top of a substrate. A polysilicon layer is overlaid on the gate oxide layer and then, a amorphous silicon layer is formed thereon. The stack of amorphous and polysilicon layers is defined to form a gate structure on gate oxide layer. Next, a thermal treatment is performed on the gate structure.

Growing community of inventors

Hsinchu, Taiwan

Hsueh-Hao Shih