Taiwan Semiconductor Manufacturing Comp. Ltd.

Hsueh-Chang Sung

Tsz-Mei Kwok

Kun-Mu Li

Chii-Horng Li

Tze-Liang Lee

Hsien-Hsin Lin

Yen-Ru Lee

Kuan-Yu Chen

Chien-Wei Lee

Yee-Chia Yeo

Chien-Chang Su

Heng-Wen Ting

Pei-Ren Jeng

Tzu-Hsiang Hsu

Feng-Cheng Yang

Ming-Huan Tsai

Chun-Fai Cheng

Yi-Fang Pai

Yan-Ting Lin

Wei-Min Liu

Wei-Han Fan

Chih-Yun Chin

Roger Tai

Davie Liu

Chih-Chiang Chang

Ming-Hua Yu

Jyun-Chih Lin

Sai-Hooi Yeong

Yen-Ming Chen

Wei-Yang Lee

Kei-Wei Chen

Sheng-Chen Wang

Weng Chang

Chun-Feng Nieh

Yen-Ting Chen

Li-Li Su

De-Wei Yu

Bo-Yu Lai

Tsung-Yao Wen

Ya-Yun Cheng

Che-Yu Lin

Chun-An Lin

Liang-Yi Chen

Hung-Yao Chen

Pin-Chu Liang

Chen-Hua Douglas Yu

Chao-Cheng Chen

Ka-Hing Fung

Han-Ting Tsai

Wei-Yuan Lu

Yimin Huang

Yu-Hsien Lin

Yu-Rung Hsu

Kuan-Chung Chen

Ming-Feng Hsieh

Chia-Ao Chang

Haiting Wang

Hsien-Ching Lo

Fung Ka Hing

Chien-Chia Cheng

A semiconductor device including a source/drain region having a V-shaped bottom surface and extending below gate spacers adjacent a gate stack and a method of forming the same are disclosed. In an embodiment, a method includes forming a gate stack over a fin; forming a gate spacer on a sidewall of the gate stack; etching the fin with a first anisotropic etch process to form a first recess adjacent the gate spacer; etching the fin with a second etch process using etchants different from the first etch process to remove an etching residue from the first recess; etching surfaces of the first recess with a third anisotropic etch process using etchants different from the first etch process to form a second recess extending below the gate spacer and having a V-shaped bottom surface; and epitaxially forming a source/drain region in the second recess.

Semiconductor device and method

A method includes forming a gate structure over fins protruding from a semiconductor substrate; forming an isolation region surrounding the fins; depositing a spacer layer over the gate structure and over the fins, wherein the spacer layer fills the regions extending between pairs of adjacent fins; performing a first etch on the spacer layer, wherein after performing the first etch, first remaining portions of the spacer layer that are within inner regions extending between pairs of adjacent fins have a first thickness and second remaining portions of the spacer layer that are not within the inner regions have a second thickness less than the first thickness; and forming an epitaxial source/drain region adjacent the gate structure and extending over the fins, wherein portions of the epitaxial source/drain region within the inner regions are separated from the first remaining portions of the spacer layer.

A method includes etching a semiconductor substrate to form a trench between a first semiconductor strip and a second semiconductor strip. The first semiconductor strip has a first width at about 5 nm below a top of the first semiconductor strip and a second width at about 60 nm below the top of the first semiconductor strip. The first width is smaller than about 5 nm, and the second width is smaller than about 14.5 nm. The trench is filled with dielectric materials to form an isolation region, which is recessed to have a depth. A top portion of the first semiconductor strip protrudes higher than the isolation region to form a protruding fin. The protruding fin has a height smaller than the depth. A gate stack is formed to extend on a sidewall and a top surface of the protruding fin.

Fin bending reduction through structure design

A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. A top portion of the semiconductor fin is formed of a first semiconductor material. A semiconductor cap layer is formed on a top surface and sidewalls of the semiconductor fin. The semiconductor cap layer is formed of a second semiconductor material different from the first semiconductor material. The method further includes forming a gate stack on the semiconductor cap layer, forming a gate spacer on a sidewall of the gate stack, etching a portion of the semiconductor fin on a side of the gate stack to form a first recess extending into the semiconductor fin, recessing the semiconductor cap layer to form a second recess directly underlying a portion of the gate spacer, and performing an epitaxy to grow an epitaxy region extending into both the first recess and the second recess.

Transistors with recessed silicon cap and method forming same

A method includes forming a fin over a substrate, forming an isolation region adjacent the fin, forming a dummy gate structure over the fin, and recessing the fin adjacent the dummy gate structure to form a first recess using a first etching process. The method also includes performing a plasma clean process on the first recess, the plasma clean process including placing the substrate on a holder disposed in a process chamber, heating the holder to a process temperature between 300° C. and 1000° C., introducing hydrogen gas into a plasma generation chamber connected to the process chamber, igniting a plasma within the plasma generation chamber to form hydrogen radicals, and exposing surfaces of the recess to the hydrogen radicals. The method also includes epitaxially growing a source/drain region in the first recess.

FinFET device and method of forming same

A method includes forming a semiconductor fin over a substrate, etching the semiconductor fin to form a recess, wherein the recess extends into the substrate, and forming a source/drain region in the recess, wherein forming the source/drain region includes epitaxially growing a first semiconductor material on sidewalls of the recess, wherein the first semiconductor material includes silicon germanium, wherein the first semiconductor material has a first germanium concentration from 10 to 40 atomic percent, epitaxially growing a second semiconductor material over the first semiconductor material, the second semiconductor material including silicon germanium, wherein the second semiconductor material has a second germanium concentration that is greater than the first germanium concentration, and epitaxially growing a third semiconductor material over the second semiconductor material, the third semiconductor material including silicon germanium, wherein the third semiconductor material has a third germanium concentration that is smaller than the second germanium concentration.

Source/drain regions of FinFET devices and methods of forming same

In an embodiment, a method includes forming a first fin and a second fin within an insulation material over a substrate, the first fin and the second fin includes different materials, the insulation material being interposed between the first fin and the second fin, the first fin having a first width and the second fin having a second width; forming a first capping layer over the first fin; and forming a second capping layer over the second fin, the first capping layer having a first thickness, the second capping layer having a second thickness different from the first thickness.

Semiconductor device and methods of manufacturing

A device includes a fin over a substrate, the fin including a first end and a second end, wherein the first end of the fin has a convex profile, an isolation region adjacent the fin, a gate structure along sidewalls of the fin and over the top surface of the fin, a gate spacer laterally adjacent the gate structure, and an epitaxial region adjacent the first end of the fin.

FinFET device and method

A semiconductor device includes a first device region and a second device region. The first device region includes a first source/drain region extending from a substrate and a first and a second pair of spacers. The first source/drain region extends between the first pair of spacers and the second pair of spacers. The first pair of spacers and the second pair of spacers have a first height. The second device region includes a second and a third source/drain region extending from the substrate and a third and a fourth pair of spacers. The third source/drain region is separate from the second source/drain region. The second source/drain region extends between the third pair of spacers. The third source/drain region extends between the fourth pair of spacers. The third pair of spacers and the fourth pair of spacers have a second height greater than the first height.

Source/drain structures and method of forming

A semiconductor device and a method of forming the same are provided. The semiconductor device includes a gate stack over an active region and a source/drain region in the active region adjacent the gate stack. The source/drain region includes a first semiconductor layer having a first germanium concentration and a second semiconductor layer over the first semiconductor layer. The second semiconductor layer has a second germanium concentration greater than the first germanium concentration. The source/drain region further includes a third semiconductor layer over the second semiconductor layer and a fourth semiconductor layer over the third semiconductor layer. The third semiconductor layer has a third germanium concentration greater than the second germanium concentration. The fourth semiconductor layer has a fourth germanium concentration less than the third germanium concentration.

Epitaxial source/drain structure and method of forming same

A method for forming a semiconductor structure includes forming a gate structure over a substrate. The method also includes forming a spacer on a sidewall of the gate structure. The method also includes forming a source/drain recess beside the spacer. The method also includes treating the source/drain recess and partially removing the spacers in a first cleaning process. The method also includes treating the source/drain recess with a plasma process after performing the first cleaning process. The method also includes treating the source/drain recess in a second cleaning process after treating the source/drain recess with the plasma process. The method also includes forming a source/drain structure in the source/drain recess after performing the second cleaning process.

Method for forming semiconductor structure

A semiconductor device having an improved source/drain region profile and a method for forming the same are disclosed. In an embodiment, a method includes etching one or more semiconductor fins to form one or more recesses; and forming a source/drain region in the one ore more recesses, the forming the source/drain region including epitaxially growing a first semiconductor material in the one or more recesses at a temperature of 600° C. to 800° C., the first semiconductor material including doped silicon germanium; and conformally depositing a second semiconductor material over the first semiconductor material at a temperature of 300° C. to 600° C., the second semiconductor material including doped silicon germanium and having a different composition than the first semiconductor material.

Semiconductor device and method of manufacture

Protective layer over FinFET and method of forming same

Embodiments provide a way of treating source/drain recesses with a high heat treatment and an optional hydrogen plasma treatment. The high heat treatment smooths the surfaces inside the recesses and remove oxides and etching byproducts. The hydrogen plasma treatment enlarges the recesses vertically and horizontally and inhibits further oxidation of the surfaces in the recesses.

Method of forming a source/drain

A fin structure on a substrate is disclosed. The fin structure can comprises a first epitaxial region and a second epitaxial region separated by a dielectric region, a merged epitaxial region on the first epitaxial region and the second epitaxial region, an epitaxial buffer region on a top surface of the merged epitaxial region, and an epitaxial capping region on the buffer epitaxial region and side surfaces of the merged epitaxial region.

Epitaxial fin structures of finFET having an epitaxial buffer region and an epitaxial capping region

Growing community of inventors

Zhubei, Taiwan

Hsueh-Chang Sung