Taiwan Semiconductor Manufacturing Comp. Ltd.

Hsu-Chieh Cheng

Ming-Yuan Wu

Ka-Hing Fung

Da-Wen Lin

Che-Yuan Hsu

Yi-Ting Fu

Min Jiao

Chen-Yu Hsieh

A method includes forming a fin protruding from a substrate, forming a first dielectric feature adjacent to the fin over the substrate, forming a cladding layer over the fin and the first dielectric feature, and removing a portion of the cladding layer to form an opening. The opening exposes the first dielectric feature. The method further includes forming a second dielectric feature adjacent to the cladding layer, the second dielectric feature filling the opening, forming a dummy gate stack over the fin and the second dielectric feature, forming source/drain (S/D) features in the fin adjacent to the dummy gate stack, and replacing the dummy gate stack and the cladding layer with a metal gate stack. The second dielectric feature divides the metal gate stack.

Method of fabricating a gate cut feature for multi-gate semiconductor devices

A method includes forming a fin structure on a substrate, forming a dummy gate structure wrapped around the fin structure, depositing an Interlayer Dielectric (ILD) layer over the fin structure, removing the dummy gate structure to expose a portion of the fin structure, and performing an etching process on the portion of the fin structure to reduce a width of the portion of the fin structure.

FinFET device with a reduced width

Growing community of inventors

Hsinchu, Taiwan

Hsu-Chieh Cheng