Micron Technology Incorporated

Inotera Memories, Inc.

Nan Ya Technology Corporation

Hsu Chiang

Neng-Tai Shih

Tzung-Han Lee

Yaw-Wen Hu

Shing-Yih Shih

Sheng-Hsiung Wu

Chung-Yuan Lee

Hsin-Chuan Tsai

Hung Chang Liao

Chung-Lin Huang

Ying-Cheng Chuang

Yu Lung Chang

Hung-Chang Liao

Lai-Cheng Tien

Ching-Yuan Kuo

Szu-Han Chen

Zhi-Yi Huang

Chih-Lin Huang

Heng Hao Hsu

A power ratchet wrench head has a gear set, a crank set, and a ratchet set. The crank set is connected to the gear set and has an outer casing and a crankshaft. The ratchet set is connected to the crank set and has a ratchet yoke, a transmission shaft, and a control knob. The transmission shaft engages with the ratchet yoke and has a pushing rod, an elastic element, a ratchet pawl, and two fixing pins. The pushing rod is disposed in the transmission shaft. The elastic element is disposed in the transmission shaft and abuts against the pushing rod. The ratchet pawl engages with the ratchet yoke and abuts against the pushing rod. The control knob is rotatably connected to the transmission shaft.

Power ratchet wrench head

A pneumatic tool has an air outlet chamber, at least one forward channel, a rear transmission spacing, at least one washer channel, at least one shaft channel, at least one bushing channel, and a front transmission chamber sequentially communicating with one another. Compressed air for driving the pneumatic motor flows into the air outlet chamber, and then flows forwardly to the front transmission chamber through the at least one forward channel, the at least one washer channel, the rear transmission spacing, the at least one shaft channel, and the least one bushing channel, sequentially. Heat produced by the pneumatic tool is continuously carried by the compressed air flowing forwardly, thereby dissipating the heat and cooling the transmission set.

Pneumatic tool

A method of forming a semiconductor structure includes following steps. A semiconductor material structure is formed over a substrate. A first pad layer is formed over the semiconductor material structure. The first pad layer and the semiconductor material structure are etched to form a trench. An oxidation process is performed on a sidewall of the semiconductor material structure to form a first oxide structure on the sidewall of the semiconductor material structure. A second oxide structure is formed in the trench.

Semiconductor structure and method of forming the same

A semiconductor device includes a substrate, and interposer layers. The substrate has a first region, and a second region adjacent the first region. The interposer layers are sequentially stacked on the substrate. Each of the interposer layers has an active region and an open region, are respectively correspond to the first region and the second region of the substrate. Each of the interposer layers includes a device layout pattern, and a stress release structure. The device layout pattern is formed within the active region. The stress release structure is formed within the open region, and includes openings.

Methods for forming semiconductor devices

A package structure and a method for fabricating thereof are provided. The package structure includes a substrate, a first connector, a redistribution layer, a second connector, and a chip. The first connector is disposed over the substrate. The redistribution layer is directly disposed over the first connector, and is connected to the substrate by the first connector. The redistribution layer includes a block layer, and a metal layer over the block layer. The second connector is directly disposed over the redistribution layer, and the chip is connected to the redistribution layer by the second connector.

Microelectronic devices including redistribution layers

The present disclosure provides a semiconductor structure and a method for forming the semiconductor structure. The semiconductor structure includes: a polysilicon layer, having a first surface and a second surface opposite to the first surface; a substrate, disposed on the second surface of the polysilicon layer; a bit line structure, disposed on the substrate, penetrating through the polysilicon layer and protruding from the first surface of the polysilicon layer; and a spacer structure, disposed on lateral sidewalls of the bit line structure, including an air gap sandwiched by a first dielectric layer and a second dielectric layer, wherein a first portion of the second dielectric layer is in the polysilicon layer, a second portion of the second dielectric layer is outside the polysilicon layer, and a thickness of the second portion of the second dielectric layer is less than a thickness of the first portion of the second dielectric layer.

Semiconductor structure and method for forming the same

Microelectronic package structures including redistribution layers

A semiconductor device includes a substrate, and interposer layers. The substrate has a first region, and a second region adjacent the first region. The interposer layers are sequentially stacked on the substrate. Each of the interposer layers has an active region and an open region, which respectively correspond to the first region and the second region of the substrate. Each of the interposer layers includes a device layout pattern, and a stress release structure. The device layout pattern is formed within the active region. The stress release structure is formed within the open region, and includes openings.

Semiconductor device

Methods of fabricating a semiconductor package structure including at least one redistribution layer

A semiconductor device includes an interposer having a first side and a second side opposite to the first side; a first semiconductor die mounted on the first side within a first chip mounting area through a plurality of first bumps; a second semiconductor die mounted on the first side within a second chip mounting area being adjacent to the first chip mounting area; a ring-shaped supporting feature disposed on the first side and encompassing the first chip mounting area and the second chip mounting area; and a plurality of solder bumps mounted on the second side.

Wafer level package with TSV-less interposer

A semiconductor device includes a semiconductor device includes an interposer having a first side and a second side opposite to the first side, wherein the interposer comprises a redistribution layer (RDL), and the RDL comprises a first passivation layer on the first side and a second passivation layer on the second side; at least one active chip mounted on the first passivation layer on the first side through a plurality of first bumps penetrating through the first passivation layer; a molding compound disposed on the first side, the molding compound covering the at least one active chip and a top surface of the first passivation layer; and a plurality of solder bumps mounted on the first passivation layer on the second side.

Wafer level package and fabrication method thereof

A semiconductor electronic device structure includes a substrate having a trench disposed therein, a gate electrode disposed in the trench, and a gate dielectric layer disposed on the surface in the trench. The substrate and the gate electrode are electrically insulated from each other by the gate dielectric layer. The substrate further has a pair of doped areas. The doped areas each are vertically disposed along the two respective lateral sides of the trench. The doped areas each have a first portion and a second portion arranged atop the first portion. The first portion extends vertically to the portion of the substrate that is aligned to the gate electrode. The lateral dimension of the first portion is smaller than the lateral dimension of the second portion, and the doping concentration of the first portion is lighter than the doping concentration of the second portion.

Semiconductor device and fabrication method therefor

A memory unit includes a substrate, at least one charge storage element, at least one first recessed access element, and an isolation portion. The substrate has a surface and the first recessed access element is disposed in an active area of the substrate and extending from the surface into the substrate. The first recessed access element is electrically connected to the charge storage element and induces in the substrate a first depletion region. The isolation portion is adjacent to the active area and extending from the surface into the substrate. The isolation portion includes a trenched isolating barrier and a second recessed access element. The second recessed access element is disposed in the trenched isolating barrier and induces in the substrate a second depletion region merging with the first depletion region.

Memory unit, memory unit array and method of manufacturing the same

A semiconductor structure includes multiple buried gates which are disposed in a substrate and have a first source and a second source, an interlayer dielectric layer covering the multiple buried gates and the substrate as well as a core dual damascene plug including a first plug, a second plug and an insulating slot. The insulating slot is disposed between the first plug and the second plug so that the first plug and the second plug are mutually electrically insulated. The first plug and the second plug respectively penetrate the interlayer dielectric layer and are respectively electrically connected to the first source and the second source.

Semiconductor structure

A semiconductor electronic device structure includes an active area array disposed in a substrate, an isolation structure, a plurality of recessed gate structures, a plurality of word lines, and a plurality of bit lines. The active area array a plurality of active area columns and a plurality of active area rows, defining an array of active areas. The substrate has two recesses formed at the central region thereof. Each recessed gate structure is respectively disposed in the recess. A protruding structure is formed on the substrate in each recess. A STI structure of the isolation structure is arranged between each pair of adjacent active area rows. Word lines are disposed in the substrate, each electrically connecting the gate structures there-under. Bit lines are disposed above the active areas, forming a crossing pattern with the word lines.

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Taipei, Taiwan

Hsu Chiang