Taiwan Semiconductor Manufacturing Comp. Ltd.

Vanguard International Semiconductor Corporation

Hsiu-Mei Yu

Chia-Jen Cheng

Wei-Chan Chang

Chang-Sheng Lin

Po-Yao Lin

Ta-Yang Lin

Ming-Chih Yew

Fu-Jen Li

Chun-Yi Wu

Cheng-Yi Hsieh

Shun-Liang Hsu

Shih-Ming Chen

Chin Kun Lan

Hung-Lin Chen

Li-Hsin Tseng

Ming-Chang Hsieh

Ken-Shen Chou

Charles Tseng

Kuo-Feng Chen

Gil Huang

Sung-Cheng Chiu

Guang-Yuan Jiang

Dong-Lung Lee

Shin-Puu Jeng

Hao-Yi Tsai

Shang-Yun Hou

Shu-Shen Yeh

Cheng-Lin Huang

Chin-Hua Wang

Hsiao-Wen Lee

Chin-Yu Ku

Kai-Ming Ching

Ta-Jen Yu

Shyue-Ter Leu

Yang-Tung Fan

Kuang-Chun Lee

Sheng-Hsiang Chiu

Tjandra Winata Karta

Wen-Hsiang Tseng

Kuang-Peng Lin

Shih-Ming Chin

Tung-Heng Shie

Chien-Tung Yu

Chun-Ying Lin

Chih-Min Tseng

Hsiu-Chieh Cheng

Young-Chang Lien

Tung-Wen Hsieh

Blenny Chang

Owen Chen

Daniel Yang

Yu-Lung Feng

Fang-Chung Liu

Fang-Chuang Liu

A semiconductor device includes: a substrate; a seed layer disposed on the substrate; a compound semiconductor stack layer disposed on the seed layer; and a source metal layer and a drain metal layer disposed on the compound semiconductor stack layer. The semiconductor device further includes a conductive layer at least partially covering the source metal layer and the drain metal layer, and covering opposing side surfaces of the seed layer and opposing side surfaces of the compound semiconductor stack layer. The conductive layer electrically connects the seed layer and the source metal layer.

Semiconductor device and method forming the same

A method for manufacturing a package structure includes providing a carrier board; providing at least one die having a top surface, a bottom surface, and a side surface on the carrier board; and forming a protective layer to cover at least a portion of the side surface of the die. The die includes a substrate, a semiconductor layer, a gate structure, a source structure and a drain structure, at least one dielectric layer, and at least one pad. The semiconductor layer is disposed on the substrate. The gate structure is disposed on the semiconductor layer. The source and the drain structures are disposed on opposite sides of the gate structure. The dielectric layer covers the gate, source, and drain structures. The pad is disposed on the dielectric layer and penetrates through the dielectric layer to electrically contact with the gate, source or drain structure.

Package structure and method for manufacturing the same

A method of forming dice includes the following steps. First, a wafer structure is provides, which includes a substrate and a stack of semiconductor layers disposed in die regions and a scribe line region. Then, the substrate and the stack of the semiconductor layers in the scribe line region are removed to form a groove in the substrate. After the formation of the groove, the substrate is further thinned to obtain the substrate with a reduced thickness. Finally, a separation process is performed on the substrate with the reduced thickness.

Method of forming dice and structure of die

A chip structure includes a substrate, a bottom conductive layer, a semiconductor layer, an interlayer dielectric layer, at least one electrode, and at least one top electrode. The substrate includes in order a core layer and a composite material. The bottom conductive layer is disposed on the bottom surface of the core layer, the semiconductor layer is disposed on the substrate, and an interlayer dielectric layer is disposed on the semiconductor layer. The at least one electrode is disposed between the semiconductor layer and the interlayer dielectric layer, and the at least one top electrode is disposed on the interlayer dielectric layer and electrically coupled to the at least one electrode.

High-efficiency packaged chip structure and electronic device including the same

A method of forming dice includes the following steps. First, a wafer structure is provides, which includes a substrate and a stack of semiconductor layers disposed in die regions and a scribe line region. Then, the substrate and the stack of the semiconductor layers in the scribe line region are removed to forma groove in the substrate. After the formation of the groove, the substrate is further thinned to obtain the substrate with a reduced thickness. Finally, a separation process is performed on the substrate with the reduced thickness.

The present disclosure provides a semiconductor structure including a first insulation, a second insulation over the first insulation, a third insulation over the second insulation, a first conductor proximal to a boundary between the first insulation and the second insulation, and an electronic device electrically connected to the first conductor and at least partially surrounded by the second insulation. A coefficient of thermal expansion (CTE) of the second insulation is larger than a CTE of the first insulation and larger than a CTE of the third insulation.

Semiconductor structure and manufacturing method thereof

An interconnect structure includes a first substrate including a first surface, a second surface opposite to the first surface, a cavity extended through the first substrate, and a first recess extended from the second surface towards the first surface; a second substrate disposed opposite to the second surface of the first substrate; an electronic device disposed within the cavity; a first polymeric layer disposed over the first surface and within the cavity of the first substrate; and a second polymeric layer disposed between the first substrate and the second substrate and within the first recess.

Interconnect structure and manufacturing method thereof

Structures and formation methods of a chip package are provided. The chip package includes a first package structure including a first semiconductor die that has a first side and a second side opposite thereto. The chip package also includes a package layer partially or completely encapsulating the first semiconductor die, and a conductive feature in the package layer. The chip package further includes a first heat-spreading layer over the first side of the first semiconductor die and a first cap layer on the first heat-spreading layer.

Chip package with thermal dissipation structure and method for forming the same

A system and method for providing a post-passivation and underbump metallization is provided. An embodiment comprises a post-passivation layer that is larger than an overlying underbump metallization. The post-passivation layer extending beyond the underbump metallization shields the underlying layers from stresses generated from mismatches of the materials' coefficient of thermal expansion.

Electrical connection for chip scale packaging

The present disclosure provides a method of making an integrated circuit (IC) device. The method includes forming a first IC feature and a second IC feature in a semiconductor substrate, the first and second IC features being spaced from each other and separated by a scribe region; forming, in the semiconductor substrate, a doped routing feature at least partially within the scribe region and configured to connect the first and second IC features; forming a multilayer interconnect (MLI) structure and an interlayer dielectric (ILD) on the semiconductor substrate, wherein the MLI is configured to be absent within the scribe region; and etching the ILD and the semiconductor substrate within the scribe region to form a scribe-line trench.

Diffusion region routing for narrow scribe-line devices

An embodiment of the disclosure includes a method of dicing a semiconductor structure. A device layer on a semiconductor substrate is provided. The device layer has a first chip region and a second chip region. A scribe line region is between the first chip region and the second chip region. A protective layer is formed over the device layer thereby over the semiconductor substrate. The protective layer on the scribe line region is laser sawn to form a notch. The notch extends into the semiconductor substrate and the protective layer is formed to cover a portion of the notch. A mechanically sawing is performed through the portion of the protective layer and the substrate to separate the first chip region and the second chip region.

Methods of dicing a semiconductor structure

An integrated circuit structure includes a passivation layer; a via opening in the passivation layer; a copper-containing via in the via opening; a polymer layer over the passivation layer, wherein the polymer layer comprises an aperture, and wherein the copper-containing via is exposed through the aperture; a post-passivation interconnect (PPI) line over the polymer layer, wherein the PPI line extends into the aperture and physically contacts the copper-via opening; and an under-bump metallurgy (UBM) over and electrically connected to the PPI line.

Back end integrated WLCSP structure without aluminum pads

Growing community of inventors

Hsinchu, Taiwan

Hsiu-Mei Yu