International Business Machines Corporation

Hsing-San Lee

John Edward Cronin

Chung H Lam

Claude Louis Bertin

Howard L Kalter

Donald M Kenney

Albert Stephan Bergendahl

John Atkinson Fifield

Norbert G Vogl, Jr

Wilbur David Pricer

Kenneth E Beilstein, Jr

Lawrence G Heller

Duane E Galbi

Charles H Stapper

A semiconductor device memory array formed on a semiconductor substrate comprising a multiplicity of field effect transistor DRAM devices disposed in array is disclosed. Each of the DRAM devices is paired with a non-volatile EEPROM cell and the EEPROM cells are disposed in a shallow trench in the semiconductor substrate running between the DRAM devices such that each DRAM-EEPROM pair shares a common drain diffusion. The EEPROM cells are arranged in the trench such that there are discontinuous laterally disposed floating gate polysilicon electrodes and continuous horizontally disposed program and recall gate polysilicon electrodes. The floating gate is separated from the program and recall gates by a silicon rich nitride. The array of the invention provides high density shadow RAMs. Also disclosed are methods for the fabrication of devices of the invention.

Process for forming a polysilicon electrode in a trench

A memory device having an on-chip ECC system includes an array of memory cells, some of which have wider transistors than others so that they have faster access speeds. Data bits are written into ordinary memory cells and the check bits are written into the faster cells in order to make up for the delay associated with the calculation of the check bits.

Fast check bit write for a semiconductor memory

Method of making shadow RAM cell having a shallow trench EEPROM

A logic system including a first logic block for providing first differential outputs; a second logic block, identical to the first logic block, for providing second differential outputs; a fault detecting device, coupled to the first logic block, for detecting a fault in the first differential outputs; and a selecting device, coupled to the first and second logic blocks and to the fault detecting device, for selecting an output of one of the first and second logic blocks depending on whether the fault detecting device detects a fault.

Fault tolerant logic system

Shadow ram cell having a shallow trench eeprom

An improved memory sensing control circuit is provided wherein pulses derived from row or word address changes and from column or bit address changes are used to produce set pulses which are applied at optimum time intervals to a sense amplifier. More particularly, the memory sensing control circuit includes first and second paths for transmitting a bit decoder drive pulse coupled to a sense amplifier set device and means responsive to pulses derived from row or word and column or bit address change detecting means for selecting one of the first and second paths.

Sense amplifier control circuit

A sensing technique or system is provided for a merged charge memory having similar storage and dummy cells with the dummy cells being charged with a reference voltage equal to 1/2 of the sum of the voltages representing 1 and 0 binary digits of information in the memory. The sensing technique or system includes an insulating layer disposed on a semiconductor substrate, a memory array having a data word line coupled to a first plurality of spaced apart conductive films formed on the insulating layer defining a plurality of data storage capacitors, sensing means having first and second terminals and a dummy line coupled to a second plurality of spaced apart conductive films formed on the insulating layer defining a plurality of reference voltage capacitors. Charge source means are coupled to the first plurality of conductive films by the word line and to the second plurality of conductive films by the dummy line. The first terminal of the sensing means is coupled to a conductive film of the first plurality of films spaced a predetermined distance from the charge source means and the second terminal of the sensing means is coupled to a given conductive film of the second plurality of films spaced the predetermined distance from the charge source means. The reference voltage is derived from the first and second terminals of the sensing means and applied to the given conductive film.

Sensing technique for memories with small cells

A merged charge memory system is provided having an accessing arrangement wherein each of the word lines of the memory array is divided into a plurality of segments with cells associated only with a selected one or a portion of the segments being coupled at any particular time to bit driving and sensing means. Thus, only relatively few sense amplifiers compared with the number of bits per word of the array are required to handle all of the cells of the array. More particularly, in the merged charge memory system of the present invention, the flow of charges from charge source means is released only to the cells of the selected word segment or segments which are simultaneously coupled to bit driving and sensing means via associated bit/sense lines.

Accessing arrangement for memories with small cells

A semiconductor memory produced in a unipolar technology includes a cell which has an inversion capacitor with one terminal connected to a bit/sense line, the other terminal is coupled to a source of charges by a pulse from a word line. The charges are produced from the source in the form of pulses injected into the capacitor. To provide a word organized array of these cells, each word includes a source of pulsed charges produced at the surface of a semiconductor substrate and a plurality of inversion capacitors are formed also at the surface of the semiconductor in spaced apart relationship from the charge source. Information is written into the capacitors by applying voltages of two different magnitudes, representing 1 and 0 bits of information, to one terminal of the capacitors while a word pulse produces inversion layers at the surface of the substrate between the capacitors to interconnect serially the pulsed charge source with each of the capacitors. The pulses of charge are timed so that they begin at least by the onset of the word pulse and terminate prior to the termination of the word pulse. Furthermore, prior to the termination of the word pulse, the voltage at the charge source is set to form a charge sink for draining excess charges. The capacitors having the larger voltage applied to the one terminal of the capacitors store the greater amount of charge. This charge can then be detected by measuring the voltage of the floating bit sense line when a word pulse again connects the charge source with each of the capacitors.

Injected charge capacitor memory

A semiconductor memory produced in a unipolar technology includes a cell which has a pair of inversion capacitors with one terminal of each capacitor connected to one of a pair of bit/sense lines, the other terminal of each capacitor is coupled to a source of charges by a pulse from a word line. The charges produced from the source may be in the form of pulses injected into the capacitors. To provide a word organized array of these cells, each word includes a source of charges produced at the surface of a semiconductor substrate and a plurality of pairs of inversion capacitors formed also at the surface of the semiconductor in spaced apart relationship from the charge source. Information is written into the pairs of capacitors by applying complementary voltages to each pair of bit/sense lines coupled to the pairs of capacitors while a word pulse produces inversion layers at the surface of the substrate between the capacitors to interconnect serially the charge source with each of the capacitors. The complementary voltages have a first and a second magnitude. When voltages of the first and second magnitudes are applied to first and second bit/sense lines, respectively, of a pair of bit/sense lines, a 1 bit of information is stored in the associated cell, and when voltages of the second and first magnitudes are applied to the first and second bit/sense lines, respectively, of the same pair of bit/sense lines, a 0 bit of information is stored in the associated cell. The capacitor of the pair of capacitors having the larger voltage applied thereto stores the greater amount of charge. By employing a differential sense amplifier and floating the pair of bit sense line when a word pulse again connects the charge source with each of the capacitors, the greater charge can be detected by noting the polarity of the different voltage between the two capacitors of the pair of capacitors.

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Essex Junction, VT, United States of America

Hsing-San Lee