Advanced Semiconductor Engineering, Inc.

Hsing Kuo Tien

Chih-Cheng Lee

Wu Chou Hsu

Min-Yao Chen

Wen Hung Huang

Chih Cheng Lee

Chien-Mei Huang

Shih-Yu Wang

I-Ting Lin

Yuh-Shan Su

Li Chuan Tsai

Chai-Chi Lin

Chih-Yung Yang

The present disclosure provides a package substrate and method of manufacturing the same. The package substrate includes a substrate, an electronic component and a conductive trace. The electronic component is disposed in the substrate, and the electronic component includes a magnetic layer and a conductive wire. The conductive wire includes a first section embedded in the magnetic layer, and a second section connected to the first section and thinner than the first section. A first upper surface of the first section is covered by the magnetic layer, a second upper surface of the second section is lower than the first upper surface, and the magnetic layer includes a first recess disposed in the upper surface and exposing the second upper surface of the second section. The first conductive trace is in the first recess and electrically connected to the second upper surface of the second section of the conductive wire.

Package substrate, electronic device package and method for manufacturing the same

A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.

Semiconductor device package including stress buffering layer

A semiconductor device package and method for manufacturing the same are provided. The semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, and a first circuit layer disposed on the substrate. The first circuit layer includes a conductive wiring pattern, and the conductive wiring pattern is an uppermost conductive pattern of the first circuit layer. The stress buffering structure is disposed on the first conductive structure. The second conductive structure is disposed over the stress buffering structure. The conductive wiring pattern extends through the stress buffering structure and electrically connected to the second conductive structure, and an upper surface of the conductive wiring pattern is substantially coplanar with an upper surface of the stress buffering structure.

Semiconductor device package and method for manufacturing the same

A package substrate and manufacturing method thereof are provided. The package substrate includes a substrate and an electronic component. The substrate includes a cavity. The electronic component is disposed in the cavity. The electronic component includes a first region and a second region, and an optical recognition rate of the first region is distinct from that of the second region.

Package substrate and method for manufacturing the same

A semiconductor device, a semiconductor device package, and a method of manufacturing a semiconductor device package are provided. The semiconductor device includes an electronic component and a first protection layer. The electronic component includes a first conductive pad protruded out of a first surface of the electronic component. The first protection layer covers an external surface of the first conductive pad. The first surface of the electronic component is exposed from the first protection layer.

Semiconductor device, semiconductor device package and method of manufacturing the same

A semiconductor device package includes a magnetically permeable layer having a top surface and a bottom surface opposite to the top surface. The semiconductor device package further includes a first conductive element in the magnetically permeable layer. The semiconductor device package further includes a first conductive via extending from the top surface of the magnetically permeable layer into the magnetically permeable layer to be electrically connected to the first conductive element. The first conductive via is separated from the magnetically permeable layer. A method of manufacturing a semiconductor device package is also disclosed.

Embedded component package structure having a magnetically permeable layer

Package substrate

The present disclosure provides a package substrate and method of manufacturing the same. The package substrate includes a substrate, an electronic component and a conductive trace. The electronic component is disposed in the substrate. The electronic component includes a conductive wire comprising an alignment mark section and a connection section, and a magnetic layer partially covering the conductive wire. The magnetic layer includes an alignment window disposed in an upper surface of the magnetic layer and exposing a first upper surface of the alignment mark section, and a recess disposed in the upper surface of the magnetic layer and exposing a second upper surface of the connection section. The conductive trace is in the recess and electrically connected to the second upper surface of the connection section of the conductive wire.

Embedded component package structure and manufacturing method thereof

Semiconductor device package with stress buffering layer and method for manufacturing the same

An embedded component package structure includes a substrate. A first conductive component extends from a first surface of the substrate to a second surface of the substrate, a first conductive layer is disposed on the first surface of the substrate, and a second conductive layer is disposed on the second surface of the substrate and is electrically connected to the first conductive layer by the first conductive component. A die is disposed in a through hole in the substrate. A back surface of the die is exposed from the second surface of the substrate. A first dielectric layer covers an active surface of the die and the first surface of the substrate. A third conductive layer is disposed on the first dielectric layer and is electrically connected to the die by a second conductive component. A first metal layer is disposed directly on the back surface of the die.

Embedded component package structure and method of manufacturing the same

A semiconductor substrate includes an interconnection structure and a dielectric layer. The dielectric layer surrounds the interconnection structure and defines a first cavity. The first cavity is defined by a first sidewall, a second sidewall, and a first surface of the dielectric layer. The first sidewall is laterally displaced from the second sidewall.

Growing community of inventors

Kaohsiung, Taiwan

Hsing Kuo Tien