Taiwan Semiconductor Manufacturing Comp. Ltd.

Ralink Technology Corporation

National Synchrotron Radiation Research Center

Hsin-Yi Lee

Chi On Chui

Cheng-Lung Hung

Weng Chang

Da-Yuan Lee

Ji-Cheng Chen

Cheng-Yen Tsai

Chi-On Chui

Ching-Hwanq Su

Huang-Lin Chao

Jia-Ming Lin

Mao-Lin Huang

Lung-Kun Chu

Chi-Cheng Hung

Yu-Sheng Wang

Kuan-Ting Liu

Wei-Chin Lee

Kun-Yu Lee

Chun-I Wu

Yen-Tien Tung

Chin-You Hsu

Zoe Chen

Hsuan-Yu Tung

Ya-Huei Li

Kuan-Yu Wang

Chung-Liang Cheng

Ming-Hsing Tsai

Harry Chuang

Chung-Chiang Wu

Chien-Wen Chen

Tzer-Min Shen

Hsiang-Pi Chang

Yu-Tai Chia

Chung-Shi Chiang

Sung-Chien Tang

Victor C Y Chang

Ching-Shun Ku

Sheng-Yung Chang

A semiconductor device including a substrate, a first transistor and a second transistor is provided. The first transistor includes a first gate structure over the first semiconductor fin. The first gate structure includes a first high-k layer and a first work function layer sequentially disposed on the substrate, a material of the first work function layer may include metal carbide and aluminum, and a content of aluminum in the first work function layer is less than 10% atm. The second transistor includes a second gate structure. The second gate structure includes a second high-k layer and a second work function layer sequentially disposed on the substrate. A work function of the first work function layer is greater than a work function of the second work function layer.

Semiconductor device and method of fabricating the same

Embodiments include a device and method of forming a device, such as a nano-FET transistor, including a first nanostructure. A gate dielectric is formed around the first nanostructure. A gate electrode is formed over the gate dielectric, and the gate electrode includes a first work function metal. In the gate electrode, a first metal residue is formed at an interface between the gate dielectric and the first work function metal as a result of a treatment process performed prior to forming the first work function metal. The first metal residue has a metal element that is different than a metal element of the first work function metal.

Gate structures in transistors and method of forming same

A method includes forming a dummy gate stack over a semiconductor region, forming a source/drain region on a side of the dummy gate stack, removing the dummy gate stack to form a trench, depositing a gate dielectric layer extending into the trench, depositing a metal-containing layer over the gate dielectric layer, and depositing a silicon-containing layer on the metal-containing layer. The metal-containing layer and the silicon-containing layer in combination act as a work-function layer. A planarization process is performed to remove excess portions of the silicon-containing layer, the metal-containing layer, and the gate dielectric layer, with remaining portions of the silicon-containing layer, the metal-containing layer, and the gate dielectric layer forming a gate stack.

NFET with aluminum-free work-function layer and method forming same

In an embodiment, a device includes: a channel region; a gate dielectric layer on the channel region; a first work function tuning layer on the gate dielectric layer, the first work function tuning layer including a n-type work function metal; a barrier layer on the first work function tuning layer; a second work function tuning layer on the barrier layer, the second work function tuning layer including a p-type work function metal, the p-type work function metal different from the n-type work function metal; and a fill layer on the second work function tuning layer.

Semiconductor device and method

A method includes forming a plurality of nanostructures over a substrate; etching the plurality of nanostructures to form recesses; forming source/drain regions in the recesses; removing first nanostructures of the plurality of nanostructures leaving second nanostructures of the plurality of nanostructures; depositing a gate dielectric over and around the second nanostructures; depositing a protective material over the gate dielectric; performing a fluorine treatment on the protective material; removing the protective material; depositing a first conductive material over the gate dielectric; and depositing a second conductive material over the first conductive.

Fluorine incorporation method for nanosheet

A method includes forming a dummy gate stack over a semiconductor region, forming a source/drain region on a side of the dummy gate stack, removing the dummy gate stack to form a trench, with the semiconductor region being exposed to the trench, forming a gate dielectric layer extending into the trench, and depositing a work-function tuning layer on the gate dielectric layer. The work-function tuning layer comprises aluminum and carbon. The method further includes depositing a p-type work-function layer over the work-function tuning layer, and performing a planarization process to remove excess portions of the p-type work-function layer, the work-function tuning layer, and the gate dielectric layer to form a gate stack.

Work-function layers in the gates of pFETs

Semiconductor devices and methods of manufacturing the semiconductor devices are disclosed herein. The methods include forming nanostructures in a multilayer stack of semiconductor materials. An interlayer dielectric is formed surrounding the nanostructures and a gate dielectric is formed surrounding the interlayer dielectric. A first work function layer is formed over the gate dielectric. Once the first work function layer has been formed, an annealing process is performed on the resulting structure and oxygen is diffused from the gate dielectric into the interlayer dielectric. After performing the annealing process, a second work function layer is formed adjacent the first work function layer. A gate electrode stack of a nano-FET device is formed over the nanostructures by depositing a conductive fill material over the second work function layer.

Semiconductor device and methods of manufacture

A device includes a semiconductor substrate; a vertically stacked set of nanostructures over the semiconductor substrate; a first source/drain region; and a second source/drain region, wherein the vertically stacked set of nanostructures extends between the first source/drain region and the second source/drain region along a first cross-section. The device further includes a gate structure encasing the vertically stacked set of nanostructures along a second cross-section. The second cross-section is along a longitudinal axis of the gate structure. The gate structure comprises: a gate dielectric encasing each of the vertically stacked set of nanostructures; a first metal carbide layer over the gate dielectric; and a gate fill material over the first metal carbide layer. The first metal carbide layer comprises Ce, Hf, V, Nb, Sc, Y, or Mo.

Transistor gate structures and methods of forming thereof

A semiconductor device includes nanosheets between the source/drain regions, and a gate structure over the substrate and between the source/drain regions, the gate structure including a gate dielectric material around each of the nanosheets, a work function material around the gate dielectric material, a first capping material around the work function material, a second capping material around the first capping material, wherein the second capping material is thicker at a first location between the nanosheets than at a second location along a sidewall of the nanosheets, and a gate fill material over the second capping material.

Gates structures of nanostructure field-effect transistors (nano-FETs) including a plurality of semiconductor based capping materials and methods of forming the same

In an embodiment, a device includes: a first nanostructure; a gate dielectric layer around the first nanostructure; a first p-type work function tuning layer on the gate dielectric layer; a dielectric barrier layer on the first p-type work function tuning layer; and a second p-type work function tuning layer on the dielectric barrier layer, the dielectric barrier layer being thinner than the first p-type work function tuning layer and the second p-type work function tuning layer.

Transistor gate structures and methods of forming the same

A device includes a first nanostructure; a second nanostructure over the first nanostructure; a high-k gate dielectric around the first nanostructure and the second nanostructure, the high-k gate dielectric having a first portion on a top surface of the first nanostructure and a second portion on a bottom surface of the second nanostructure; and a gate electrode over the high-k gate dielectric. The gate electrode comprises: a first work function metal around the first nanostructure and the second nanostructure, the first work function metal filling a region between the first portion of the high-k gate dielectric and the second portion of the high-k gate dielectric; and a tungsten layer over the first work function metal, the tungsten layer being free of fluorine.

Transistor gate structure and method of forming

The present disclosure provides a semiconductor structure and a method for forming the same. The semiconductor structure includes a first nanosheet channel structure and a first high-k dielectric layer surrounding the first nanosheet channel structure. In addition, the semiconductor structure includes a second nanosheet channel structure disposed above and substantially parallel to the first nanosheet channel structure, and a second high-k dielectric layer surrounding the second nanosheet channel structure. The semiconductor structure further includes a work function adjustment layer including silicon and disposed between the first high-k dielectric layer and the second high-k dielectric layer. The first high-k dielectric layer and the second high-k dielectric layer are separated by the work function adjustment layer.

Semiconductor structure including nanosheet channel structure and method for forming the same

The present disclosure describes a method for forming a semiconductor device having a work function metal layer doped with tantalum to mitigate oxygen diffusion and improve device threshold voltage. The method includes forming a gate dielectric layer on a channel structure and forming a work function metal layer on the gate dielectric layer. The gate dielectric layer includes an interfacial layer on the channel structure and a high-k dielectric layer on the interfacial layer. The method further includes doping the work function metal layer and the gate dielectric layer with tantalum.

Work function tuning in semiconductor devices

A semiconductor device includes a fin protruding above a substrate; source/drain regions over the fin; nanosheets between the source/drain regions; and a gate structure over the fin and between the source/drain regions. The gate structure includes: a gate dielectric material around each of the nanosheets; a first liner material around the gate dielectric material; a work function material around the first liner material; a second liner material around the work function material; and a gate electrode material around at least portions of the second liner material.

Nanosheet field-effect transistor device and method of forming

A semiconductor device and a method of forming the same are provided. The method includes forming a fin extending from a substrate. A dummy gate is formed over the fin. The dummy gate extends along sidewalls and a top surface of the fin. The dummy gate is removed to form a recess. A replacement gate is formed in the recess. Forming the replacement gate includes forming an interfacial layer along sidewalls and a bottom of the recess. A dipole layer is formed over the interfacial layer. The dipole layer includes metal atoms. Fluorine atoms are incorporated in the dipole layer. The fluorine atoms and the metal atoms are driven from the dipole layer into the interfacial layer. The dipole layer is removed.

Growing community of inventors

Hsinchu, Taiwan

Hsin-Yi Lee