United Microelectronics Corp.

Hsin Tai

Chung-Ju Lee

Nien-Chung Li

Chih-Ning Wu

Wei-Tsun Shiau

Ming-Shing Chen

Li-Shiun Chen

Hui-Ling Huang

A method for manufacturing MOS transistor with hybrid hard mask includes providing a substrate having a dielectric layer and a polysilicon layer thereon, forming a hybrid hard mask having a middle hard mask and a spacer hard mask covering sidewalls of the middle hard mask on the polysilicon layer, performing a first etching process to etch the polysilicon layer and the dielectric layer through the hybrid hard mask to form a gate structure, performing a second etching process to form recesses in the substrate at two sides of the gate structure, and performing a SEG process to form epitaxial silicon layers in each recess.

Method for manufacturing MOS transistors utilizing a hybrid hard mask

A method of fabricating strained-silicon transistors includes providing a semiconductor substrate, in which the semiconductor substrate contains a gate structure thereon; performing an etching process to form two recesses corresponding to the gate structure within the semiconductor substrate; performing an oxygen flush on the semiconductor substrate; performing a cleaning process on the semiconductor substrate; and performing a selective epitaxial growth (SEG) to form an epitaxial layer in each recess for forming a source/drain region.

Method of fabricating strained-silicon transistors and strained-silicon CMOS transistors

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Taipei, Taiwan

Hsin Tai