Taiwan Semiconductor Manufacturing Comp. Ltd.

Hsin-Pai Chen

Pei-Hung Chen

An-Min Chiang

Yung-Haw Liaw

Dong-Shiuh Cheng

Chih-Shih Wei

Ching-Tang Tsai

Yen-Lung Chiu

Tien-Chen Chang

Sue-Mei Ku

A method of forming a number of closely spaced electrodes is described wherein covering the electrodes with a conformal layer of oxide or nitride deposited using plasma enhanced chemical vapor deposition does not result in the formation of restricted regions or keyholes between adjacent electrodes. The method uses de-focussing to form the electrode mask pattern in a layer of photoresist. The focal plane in which the electrode pattern is focussed is positioned a de-focus distance above the layer of photoresist. The de-focus method results in electrodes having a trapezoidal cross section wherein the bottom of the electrode is wider than the top of the electrode. The trapezoidal cross section avoids the formation of restricted regions or keyholes when the electrodes are covered with a conformal dielectric layer, such as a layer of oxide or nitride deposited using plasma enhanced chemical vapor deposition.

Opposite focus control to avoid keyholes inside a passivation layer

A method for forming a polycide/oxide/polysilicon capacitor on a silicon wafer with improved dielectric stability and reliability is described wherein an in-situ high temperature anneal is applied to the wafer within a CVD reactor immediately prior to the deposition of the silicon oxide capacitor dielectric layer. The in-situ anneal causes sufficient fluorine outgassing of the polycide layer to prevent fluorine degradation of the subsequently deposited oxide capacitor dielectric. The capacitance of the completed capacitor is increased by as much as 10% when compared to a comparable not in-situ anneal conducted prior to the insertion of the wafer into the CVD reactor.

Procedure for elimating flourine degradation of WSi.sub.x

A method is described whereby a wafer having a layer of photoresist on its surface, can be subjected to ion implantation just prior to examination by a scanning-electron-microscope(SEM) thereby rendering the photoresist sufficiently conductive that charging of the surface does not occur within the SEM. Accumulation of surface charge on specimens in the SEM causes gross image distortion and obliteration. The technique is particularly useful for inspecting a developed photoresist layer on an insulating layer such as silicon oxide prior to oxide etching. Such is the case when the wafer is being inspected for photoresist quality and pattern dimensions prior to contact opening. The resist mask is developed and subjected to a low dosage ion implant. Images are rendered crisp and clear allowing for accurate measurements. The ability to test the photo pattern at this point is cost effective in that it permits the option of photoresist re-work, and lessens the need for a post-etch inspection.

Method for eliminating charging of photoresist on specimens during

The present invention is a method of manufacturing a high/low resistance on a mix-mode product. The method includes forming a polysilicon layer over a wafer. A blanket ion implantation is performed to implant ions into the entire polysilicon layer. The polysilicon layer is then separated into a high resistance area and a low resistance area. The low resistance area top surface is raised higher than the high resistance area. A photoresist is then formed on the polysilicon areas. The photoresist is subsequently etched back to the top surface of the low resistance areas. A second implant is done on the low resistance area.

Method of forming a semiconductor device having high and low resistance

A method of forming capacitors comprising polysilicon, polysilicon oxide, metal is described which significantly improves uniformity of capacitance across the silicon integrated circuit wafer and avoids damage to electrical contact regions. A first layer of polysilicon oxide is formed on a polysilicon first capacitor plate. The wafer is then dipped in a buffered oxide etch or subjected to a dry anisotropic etch. The etching conditions the polysilicon layer so that subsequent polysilicon oxide growth is very uniform and controllable. A second polysilicon oxide layer is then formed on the polysilicon first capacitor plate. A layer of silicon nitride is formed on the polysilicon oxide and a second capacitor plate is formed on the layer of silicon nitride completing the capacitor. Improved capacitance uniformity across the wafer is achieved and device damage is avoided.

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Hsin-Chu, Taiwan

Hsin-Pai Chen